A LINEAR CMOS OTA FOR VHF APPLICATI

Stanislaw SZCZEPANSKI, Jacek JAKUSZ Rolf SCHAUMANN

Faculty of Electronics Dept. of Electrical Engineering
Technical University of Gdalisk Portland State University
80-952 Gdafisk, Poland Portland, OR 97207-075 1
Phone: 48-58-47-22-78 FAX: 48-58-47-23-78 Phone: 503-725-3806 FAX: 725-321 1
e.maili: [email protected] e.mai1: [email protected]

ABSTRACT - The design of a linear, fully-balanced, parators [2], and to construct a Q-control loop in
voltage-tunable CMOS operational transconductance monolithic filters based on gm - C topology [l].
amplifier (OTA) with improved gain and very wide In this paper, a VHF CMOS OTA is proposed
bandwidth is described. It uses a cross-coupled, two- with a negative resistor as an active load in the g,
differential-pair transconductor together with a nega- stage to enhance the dc gain.
tive resistance load for compensating the parasitic
output resistance of the OTA. Since no additional 11. CMOS OTA-C INTEGRATOR WITH NRL
internal nodes are generated dc-gain enhancement is
obtained without any bandwidth limitation. SPICE A. Linearized Transconductor
simulation results show THD < 1% at 1.9Vp, with An MOS transconductor is described in [ 3 ]
dynamic range equal to 63dB at a power consumption where, using a bias offset technique, a perfectly linear
of 2.7mW from a single 5-V supply. Application to a transfer characteristic is obtained from two cross-
lowpass filter in the VHF range is presented as an coupled differential pairs operating in saturation.
example, assuming implementation in a standard 2 However, the two real voltage shifters in 131 introduce
pm CMOS process (MOSIS). The cutoff frequency two additional internal nodes resulting in bandwidth
of the filter is tunable in the range of 8.3 - 50.0 MHz. limitation.
An alternative technique for a CMOS OTA
I. INTRODUCTION based on two cross-coupled differential nMOS pairs
Many design techniques have been proposed M i , M2, and M3, M4 is shown in Fig. 1. The identi-
for transconductors for very-high-frequency (VHF) cal MOS devices M1 - M4 operate in saturation, and
appIications. Most often the transconductance- both pairs are biased by a dc current sink 210 in com-
capacitor (gm - C ) approach is used for the basic bination with a floating voltage source VB with a low
building block, a continious-time integrator, for which output resistance rnur.V B is connected between nodes
a key prefomance parameter is the phase shift at its c and d. Thus, this topology of the transconductor
unity-gain frequency. Deviations from the ideal -90" circuit (ideally with rour= 0) does not introduce addi-
phase of the integrator are mainly due to finite dc gain tional internal nodes resulting in improved high-
and parasitic poles of the g, circuit [l]. The fre- frequency performance. In the range of operation the
quency response of high-frequency filters, e.g., is very current 210 is assumed constant and tuning is achieved
sensitive to extra phase shifts in the integrator. There- by adjusting VB (Fig. 2).
fore, to avoid deviations in filter characteristics, a Using the standard square-law model for MOS
high-dc-gain integrator is required with parasitic poles devices, the currents 11and 12, defined in Fig. 1, are:
located much higher than the filter cutoff frequency to
keep the integrator phase at -90". II = kn ( V p - VTn ) 2 + k n (VQ - VB - VTn l2 (1)
In the design of transconductors much effort 12 = kn (VQ - VTn )2 + k n (VP - V B - VTn >2 (2)
has been placed on achieving high output resistance
where kn = 0 . 5 C,, ~ ~W / L is the transconductance
(high de gain). A design technique based on the use
of negative resistance elements without any
parameter, and pn, C ,,, V T ~W, and L have their
usual meaning. V p and VQ are the gate-source vol-
bandwidth penalty was reported in the literature [4],
[5], [6]. It leads to an integrator with theoretically tages of MI and M2, respectively. With (1) and (2),
infinite dc gain and large bandwidth. This technique, the differential small-signal output current
has also been used to improve gain performance and I,,, = 1 1 - 1 2 can be expressed in terms of the VB as
for minimizing propagation delay of clamped com- I,,,, = I 1 -12=2knVg(Vp -V~)=2k,VgV;d ( 3 )
This work was supported in part by the State Scientific Research where V;d = Vp - VQ is the differential input voltage.
Committee, Poland, grant No. 8 S O 1 024 07, and by the National Thus, the transconductor stage exhibits a perfectly
Science Foundation, USA, grant No. MIP 91-21360. linear transconductance, g, = 2kn VB, which is tun-
able by varying VB. It is assumed that the input signal

0-7803-2570-2/95 $4.00 01995 IEEE 1344

is fully balanced around a common-mode value Under the assumptions that VA is positive and
vic VA a V D, from
~ ( 5 ) the equivalent negative resistance
RN is
,
NRL circuit
VA

I VDD

-
-- 1 ____ - 1
gmX-gmS gml-gm6
M5 M7 M8 M6
and is perfectly linear if second-order effects are
neglected. The element can be tuned by varying the
difference V D -~V,. Eq. ( 6 ) is valid as long as M5
through M8 operate in saturation; thus the range of
V,,, is limited by: I V,,, I I 1 V , , I and

where I o = (I, + I b f l is the dc bias current flowing

out of the NRL circuit at riodes a and b. Note also
that all transistors M5 - It48 will be operating in
saturation only if the CM voltages at the output termi-
Fig. 1. Simplified scheme of the CMOS OTA-C nals are kept less than VA -1 VT,, I . The NRL element
integrator with a voltage-variable N R L circuit. results in a large differential-mode gain; however, it
can be shown that the small-signal CM load resistance
seen from nodes a and b is small,

so that CM gain is small and no CM rejection circui-

try is needed.

C. Frequency Response and Stability Margin.

Fig. 3 shows the small-signal model of the
-
4
00
-2 half-circuit equivalent for frequency analysis of the
-1.5 -1.0 -0.5 0 0.5 1.0 1.5
Vs M OTA-C integrator in Fig. 1. In this model it is
Fig. 2. Tuning capability of the CMOS; OTA element assumed that the widths W ! = W2 = W3 = W4. result-
in Fig. 4; V, is taken as paramenter. ing in CRdi= CRd,i = 1, ...,4.

Similar to the derivation in [3], for the transis-

tors MI - M4 to operate in saturation the linear range
of V;,J is limited by
I vid I _<dIdk,- (314)v&- b'B n (4)
which requires that the CM voltages
V;, 2 V , , + V , + V D ~ where
~ ~ , , V D S ~is~the
, minimum
voltage required for the current source 210 to operate
in saturation. Fig. 3 . Simplified small-signal model of the half-circuit
B. Voltage-Controllable NRL Applying this model, the transfer function is given by
Consider the negative resistance load (NRL)
subcircuit in Fig. 1. Applying again the square-law
characteristic for devices M5-M8, the current differ-
ence 1, - It,,can be shown to be equivalent of the OTA-C integrator in Fig. 1.
1, - It,,= 2kp (VA - VDD)vou, (5) where the parameters of the model are defined as
where V,,, = vb - Vu is the differential output vol- g m =gml -gm4=2knV~ (10)
tage, and all undefined parameters have their usual
meaning. Cl = c,, 1 + C g s 3 + 2C,d (1 1)

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 &b = c d . 1~ c d . 4~ c d .5~$- c d ,8~+ Cg.7 5 ( 12, nonsaturation or saturation.
+ c g s 7 + 2C,d + 2C,dl+ 2Cgd8
In Fig. 4 a non-ideal voltage source with
r,,, 2 1.4kR is composed of transistors Mal-Ma3 and
RP = 1 + SO4 + + g08) (13) Mbl-Mb3. The source-coupled pair M a l , Ma2
and RN is given in (6). g,J;= Ih,,; are the output con- together with two current sources 1s and ICF act as a
ductances of the MOS transistors. Under the condi- simple voltage shifter in the low-gain negative feed-
tion RN =-Rp Eq. (9) indicates a theoretically back loop containing Mal through Ma3. Thus VB can
infinite dc gain. The maximal dc gain of the integra- be approximated as
tor is only limited by mismatch. .To avoid instability
problems in the circuit in Fig. 1, it is seen from (9)
with (6) and (13) that V, should be limited by
By (1 5) V, depends on the bias currents 1, and IC,.
In Fig. 4 the current 1s > ICF is held constant and VB
is controlled by varying the current ICF. 1s is
The dc gain of the integrator is controlled by the obtained from the current mirror (Mbl-Mb3) while
difference V D -~ VA ; such tuning during operation is the current source ICF is assumed to be ideal. MI-M4
desirable to obtain better accuracy in filter response form the g, stage and Mb4 acts as current sink 210.
(Q-tuning) [ 11. Note that the NRL element (M5-M9) is adjusted by
The above considerations demonstrate that varying the bias voltage VCQ at the gate of M9. Also
loading the output of the integrator in Fig. 1 with a note that in this OTA without CM feedback circuitry
voltage-variable NRL element yields high dc gain and good stabilization of the CM output voltage is
very large bandwidth due to the absence of extra obtained: simulated changes of the output current
internal nodes, which results in the equivalent non- over the OTA's whole tuning range do not affect the
dominant pole being located above 10 GHz (Fig. 6). dc output voltage by more than 22mV.

~ viuisv

- .. .. __
Transconductance range 67 -403 CLS;
- gain
DC voltage - > 67 dB
Integrated input noise (1-50 MHz
@ ICF = 14 M ) 76FvRMS
THD (vjd = 1.4OVp-p @ IO MHZ
and ICF = 14 ryi -40 dB
Dynamic range (THD = -40 d B ,
@ 10 MHZ and ICF = 14 @ ) 76 dB
CMRR@ 50 MHz 52 dB
PSRR+ @ 50 MHz 61 dB
Equivalent diff. C;, 0.065 p F
Equivalent diff. CO,, 0.033 p F
Fig. 4 Complete circuit diagram of the simulated
Power consumption 2.7 mW
CMOS OTA with the NRL

111. SIMULATION RESULTS SPICE simulation shows that THD < 1% for an input
A. Voltage-tunable CMOS OTA voltage 1.9VP, at V, = 0.08V and g, can be tuned
from 67pS to 4 0 3 G as the current ICF is changed
The CMOS OTA in Fig. 4, based on the circuit from 2pA to 14p.4. The dc voltage gain of the pro-
in Fig. 1, was designed and simulated using SPICE posed OTA can be kept above 68dB over the whole
Level 2 models and 2pm MOSFETs with VT,, = tuning range by varying the control voltage V ~ Qfrom
0.863V, V T ~= -8.963V, and k,, =47.40p.4N2, kol, 1.95V to 1.70V. Fig. 5 shows the simulated gain and
= 17.10p.4N2. A11 p-channel transistors have their phase response of the OTA-C integrator when the
bulks connected to VDD. The bulks of all n-channel OTA in Fig. 4 is loaded with C, = 0.5pF. It is seen
transistors are connected to their source terminals, that high dc gain can be obtained with parasitic poles
except M3 and M4 which have their bulks connected located beyond IOGHz . Other important characteris-
to the common-source node of M1 and M2. Ml-M8, tics of the OTA circuit in Fig. 4 are summarized in
Mal-Ma2 and MDI-Mb4 work in saturation, while Table 1, where the worst-case CMRR and worst-case
M9 is biased in nonsaturation and Ma3 may operate in

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PSRR have been simulated assuming equal 0.5%
mismatches in the parameters kn , k,, , VT,, and VT, of
all MOS devices.

<1> VQ
<2> ii 1.700v

1.0 3.0 10 30 100 300

Fkquency (MHzl

Fig. 5 Simulated gain and phase responses of the Fig. 6. Simulated response of the 3rd-order filter.
OTA-C integrator in Fig. 4 for fixed ICF = 14pA ;
V c ~ i taken
s as paramenler IV. CONCLUSIONS
B. Filter Example.
A fully-balanced tunable CMOS OTA with
As an example, a third-order OTA-C elliptic improved gain for VHF applications is described.
filter ladder [ 11, [4] has been designeld and simulated The circuit has low distortion, and very wide
using the integrator of Fig. 4. bandwidth. It uses two cross-coupled differential
Changing ICF from 2pA to 14+4 and conse- pairs together with a negative resistance load for com-
quently V, from 0.08V to 0.63V, the cutoff frequency pensation of the parasitic output resistance of the
of the filter is tuned in the range 8.3 - 50.0 MHz (Fig. OTA. Since no additional internal nodes are gen-
6). Other simulation results are showri in Table 2. erated, dc gain enhancement is obtained without any
In the filter, adjustment of ZCF (frequency tun- bandwidth limitations. The: application of the OTA to
ing) and VCQ (Q-tuning) was performed manually; a third-order elliptic lOWpiSS filter with a cutoff fre-
therefore, very close agreement between theoretical quency up to 50 MHz is ]presented assuming imple-
predictions and simulated performance as shown in mentation in a standard 2 pm CMOS process.
Fig. 6 can be observed. In practice, due to process
and temperature variations, additional circuitry for REFERENCES
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315-317, Feb. 1990.
[4] B. Nauta, "A CMOS transconductance-C filter
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[SI G.A. De Veirman and R.G. Yamasaki, "Design
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