LLVM 20.0.0git
MachineSSAContext.cpp
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1//===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file defines a specialization of the GenericSSAContext<X>
11/// template class for Machine IR.
12///
13//===----------------------------------------------------------------------===//
14
22
23using namespace llvm;
24
25template <>
27 const MachineBasicBlock &block) {
28 for (auto &instr : block.instrs()) {
29 for (auto &op : instr.all_defs())
30 defs.push_back(op.getReg());
31 }
32}
33
34template <>
37 for (auto &T : block.terminators())
38 terms.push_back(&T);
39}
40
41template <>
44 const MachineBasicBlock &block) {
45 for (auto &T : block.terminators())
46 terms.push_back(&T);
47}
48
49/// Get the defining block of a value.
50template <>
52 if (!value)
53 return nullptr;
54 return F->getRegInfo().getVRegDef(value)->getParent();
55}
56
57static bool isUndef(const MachineInstr &MI) {
58 return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
59 MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
60}
61
62/// MachineInstr equivalent of PHINode::hasConstantOrUndefValue() for G_PHI.
63template <>
65 if (!Phi.isPHI())
66 return false;
67
68 // In later passes PHI may appear with an undef operand, getVRegDef can fail.
69 if (Phi.getOpcode() == TargetOpcode::PHI)
70 return Phi.isConstantValuePHI();
71
72 // For G_PHI we do equivalent of PHINode::hasConstantOrUndefValue().
73 const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo();
74 Register This = Phi.getOperand(0).getReg();
75 Register ConstantValue;
76 for (unsigned i = 1, e = Phi.getNumOperands(); i < e; i += 2) {
77 Register Incoming = Phi.getOperand(i).getReg();
78 if (Incoming != This && !isUndef(*MRI.getVRegDef(Incoming))) {
79 if (ConstantValue && ConstantValue != Incoming)
80 return false;
81 ConstantValue = Incoming;
82 }
83 }
84 return true;
85}
86
87template <>
89 if (auto *GI = dyn_cast<GIntrinsic>(&MI))
90 return GI->getIntrinsicID();
92}
93
94template <>
96 if (!Block)
97 return Printable([](raw_ostream &Out) { Out << "<nullptr>"; });
98 return Printable([Block](raw_ostream &Out) { Block->printName(Out); });
99}
100
101template <> Printable MachineSSAContext::print(const MachineInstr *I) const {
102 return Printable([I](raw_ostream &Out) { I->print(Out); });
103}
104
106 auto *MRI = &F->getRegInfo();
107 return Printable([MRI, Value](raw_ostream &Out) {
108 Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI);
109
110 if (Value) {
111 // Try to print the definition.
112 if (auto *Instr = MRI->getUniqueVRegDef(Value)) {
113 Out << ": ";
114 Instr->print(Out);
115 }
116 }
117 });
118}
119
120template <>
122 return Printable([BB](raw_ostream &Out) { BB->printAsOperand(Out); });
123}
unsigned const MachineRegisterInfo * MRI
Given that RA is a live value
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
#define op(i)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
static bool isUndef(const MachineInstr &MI)
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unify loop Fixup each natural loop to have a single exit block
static void appendBlockDefs(SmallVectorImpl< ValueRefT > &defs, BlockT &block)
static bool isConstantOrUndefValuePhi(const InstructionT &Instr)
static void appendBlockTerms(SmallVectorImpl< InstructionT * > &terms, BlockT &block)
static Intrinsic::ID getIntrinsicID(const InstructionT &I)
Printable print(const BlockT *block) const
const BlockT * getDefBlock(ConstValueRefT value) const
Printable printAsOperand(const BlockT *BB) const
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Representation of each machine instruction.
Definition: MachineInstr.h:71
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
void push_back(const T &Elt)
Definition: SmallVector.h:413
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
NodeAddr< InstrNode * > Instr
Definition: RDFGraph.h:389
NodeAddr< PhiNode * > Phi
Definition: RDFGraph.h:390
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...