29 for (
auto &
op :
instr.all_defs())
37 for (
auto &
T :
block.terminators())
45 for (
auto &
T :
block.terminators())
54 return F->getRegInfo().getVRegDef(
value)->getParent();
58 return MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
59 MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
69 if (
Phi.getOpcode() == TargetOpcode::PHI)
70 return Phi.isConstantValuePHI();
76 for (
unsigned i = 1, e =
Phi.getNumOperands(); i < e; i += 2) {
79 if (ConstantValue && ConstantValue !=
Incoming)
89 if (
auto *GI = dyn_cast<GIntrinsic>(&
MI))
90 return GI->getIntrinsicID();
106 auto *
MRI = &F->getRegInfo();
112 if (
auto *Instr =
MRI->getUniqueVRegDef(
Value)) {
unsigned const MachineRegisterInfo * MRI
Given that RA is a live value
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
static bool isUndef(const MachineInstr &MI)
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unify loop Fixup each natural loop to have a single exit block
static void appendBlockDefs(SmallVectorImpl< ValueRefT > &defs, BlockT &block)
static bool isConstantOrUndefValuePhi(const InstructionT &Instr)
static void appendBlockTerms(SmallVectorImpl< InstructionT * > &terms, BlockT &block)
static Intrinsic::ID getIntrinsicID(const InstructionT &I)
Printable print(const BlockT *block) const
const BlockT * getDefBlock(ConstValueRefT value) const
Printable printAsOperand(const BlockT *BB) const
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
NodeAddr< InstrNode * > Instr
NodeAddr< PhiNode * > Phi
This is an optimization pass for GlobalISel generic memory operations.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Incoming for lane maks phi as machine instruction, incoming register Reg and incoming block Block are...