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Merged
merged 21 commits into from
Mar 24, 2024
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bb4bba5
Remove redundant imports
taiki-e Feb 22, 2024
8c786f3
Merge pull request #397 from taiki-e/imports
calebzulawski Feb 22, 2024
6ce3ab7
Fix build error on big endian aarch64
taiki-e Feb 22, 2024
94f4f68
Merge pull request #396 from taiki-e/aarch64-big
calebzulawski Feb 22, 2024
18de239
add stdarch_x86_avx512 feature flag for AVX-512-supporting architectures
AquaEBM Feb 23, 2024
fbc9efa
Merge pull request #398 from AquaEBM/avx512-feature-flag
calebzulawski Feb 23, 2024
499a53d
feat: add SIMD float math functions (exp, exp2, log, log2, log10, sin…
Mar 3, 2024
eea6f77
Merge pull request #400 from avhz/master
calebzulawski Mar 3, 2024
5b5b259
Test std_float
calebzulawski Mar 3, 2024
e5d5006
Update docs
calebzulawski Mar 3, 2024
bcedde5
Fix formatting
calebzulawski Mar 3, 2024
2f062b8
Fix wasm tests
calebzulawski Mar 3, 2024
278eb28
Attempt to avoid LLVM error
calebzulawski Mar 3, 2024
5794c83
Merge pull request #401 from rust-lang/std_float_improvements
calebzulawski Mar 6, 2024
ca4033f
Add arm64ec support
dpaoliello Feb 23, 2024
4f0ba1a
Add support for masked loads & stores
farnoy Feb 29, 2024
6aeff2e
Merge pull request #404 from dpaoliello/arm64ec
calebzulawski Mar 14, 2024
50e8ae8
Merge pull request #399 from farnoy/masked-load-store-simple
calebzulawski Mar 14, 2024
53de3f0
Use v1 prelude to match core (rust-lang/portable-simd#406)
calebzulawski Mar 22, 2024
cff979e
Validate generating docs (rust-lang/portable-simd#407)
dpaoliello Mar 22, 2024
9e0ec25
Merge commit 'cff979eec1ac0473fc4960ee6cde462c6aeda824' into sync-por…
dpaoliello Mar 22, 2024
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Add arm64ec support
  • Loading branch information
dpaoliello committed Mar 7, 2024
commit ca4033f49b1f6019561b8b161b4097b4a07f2e1b
2 changes: 1 addition & 1 deletion crates/core_simd/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@
)]
#![cfg_attr(
all(
any(target_arch = "aarch64", target_arch = "arm",),
any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm",),
any(
all(target_feature = "v6", not(target_feature = "mclass")),
all(target_feature = "mclass", target_feature = "dsp"),
Expand Down
8 changes: 6 additions & 2 deletions crates/core_simd/src/swizzle_dyn.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,10 @@ where
#[inline]
pub fn swizzle_dyn(self, idxs: Simd<u8, N>) -> Self {
#![allow(unused_imports, unused_unsafe)]
#[cfg(all(target_arch = "aarch64", target_endian = "little"))]
#[cfg(all(
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
))]
use core::arch::aarch64::{uint8x8_t, vqtbl1q_u8, vtbl1_u8};
#[cfg(all(
target_arch = "arm",
Expand All @@ -37,6 +40,7 @@ where
#[cfg(all(
any(
target_arch = "aarch64",
target_arch = "arm64ec",
all(target_arch = "arm", target_feature = "v7")
),
target_feature = "neon",
Expand All @@ -48,7 +52,7 @@ where
#[cfg(target_feature = "simd128")]
16 => transize(wasm::i8x16_swizzle, self, idxs),
#[cfg(all(
target_arch = "aarch64",
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_feature = "neon",
target_endian = "little"
))]
Expand Down
2 changes: 1 addition & 1 deletion crates/core_simd/src/vendor.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ mod x86;
#[cfg(target_arch = "wasm32")]
mod wasm32;

#[cfg(any(target_arch = "aarch64", target_arch = "arm",))]
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec", target_arch = "arm",))]
mod arm;

#[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))]
Expand Down
8 changes: 6 additions & 2 deletions crates/core_simd/src/vendor/arm.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,13 @@ use crate::simd::*;
#[cfg(target_arch = "arm")]
use core::arch::arm::*;

#[cfg(target_arch = "aarch64")]
#[cfg(any(target_arch = "aarch64", target_arch = "arm64ec"))]
use core::arch::aarch64::*;

#[cfg(all(
any(
target_arch = "aarch64",
target_arch = "arm64ec",
all(target_arch = "arm", target_feature = "v7"),
),
target_endian = "little"
Expand Down Expand Up @@ -69,7 +70,10 @@ mod simd32 {
from_transmute! { unsafe Simd<i8, 4> => int8x4_t }
}

#[cfg(all(target_arch = "aarch64", target_endian = "little"))]
#[cfg(all(
any(target_arch = "aarch64", target_arch = "arm64ec"),
target_endian = "little"
))]
mod aarch64 {
use super::neon::*;
use super::*;
Expand Down