Skip to content
View niexun725's full-sized avatar
  • Xidian University
  • Xi'an

Block or report niexun725

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. openofdm openofdm Public

    Forked from jhshi/openofdm

    Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

    Verilog

  2. Butterfly_Acc Butterfly_Acc Public

    Forked from hmarkc/Butterfly_Acc

    The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"

    Verilog

  3. switchboard switchboard Public

    Forked from zeroasiccorp/switchboard

    Communication framework for RTL simulation and emulation.

    Python

  4. umi umi Public

    Forked from zeroasiccorp/umi

    Universal Memory Interface (UMI)

    Verilog

  5. aib-phy-hardware aib-phy-hardware Public

    Forked from chipsalliance/aib-phy-hardware

    Advanced Interface Bus (AIB) die-to-die hardware open source

    Verilog

  6. ravenoc ravenoc Public

    Forked from aignacio/ravenoc

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

    SystemVerilog