[InstCombine] Fold fneg/fabs patterns with ppc_f128 #130557

dtcxzyw · 2025-03-10T07:39:26Z

This patch is needed by #130496.

llvmbot · 2025-03-10T07:39:57Z

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Author: Yingwei Zheng (dtcxzyw)

Changes

This patch is needed by #130496.

Full diff: https://github.com/llvm/llvm-project/pull/130557.diff

4 Files Affected:

(modified) llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (+13-22)
(modified) llvm/test/Transforms/InstCombine/fabs-as-int.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/fneg-as-int.ll (+2-2)
(modified) llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll (+3-2)

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 6cc241781d112..8394cbb5e3183 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2637,18 +2637,15 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
   // This is a generous interpretation for noimplicitfloat, this is not a true
   // floating-point operation.
   //
-  // Assumes any IEEE-represented type has the sign bit in the high bit.
+  // Assumes any floating point type has the sign bit in the high bit.
   // TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
   Value *CastOp;
   if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
-      match(Op1, m_MaxSignedValue()) &&
+      CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_MaxSignedValue()) &&
       !Builder.GetInsertBlock()->getParent()->hasFnAttribute(
           Attribute::NoImplicitFloat)) {
-    Type *EltTy = CastOp->getType()->getScalarType();
-    if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
-      Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
-      return new BitCastInst(FAbs, I.getType());
-    }
+    Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
+    return new BitCastInst(FAbs, I.getType());
   }
 
   // and(shl(zext(X), Y), SignMask) -> and(sext(X), SignMask)
@@ -4047,21 +4044,18 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
   // the number of instructions. This is still probably a better canonical form
   // as it enables FP value tracking.
   //
-  // Assumes any IEEE-represented type has the sign bit in the high bit.
+  // Assumes any floating point type has the sign bit in the high bit.
   //
   // This is generous interpretation of noimplicitfloat, this is not a true
   // floating-point operation.
   Value *CastOp;
   if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
-      match(Op1, m_SignMask()) &&
+      CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
       !Builder.GetInsertBlock()->getParent()->hasFnAttribute(
           Attribute::NoImplicitFloat)) {
-    Type *EltTy = CastOp->getType()->getScalarType();
-    if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
-      Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
-      Value *FNegFAbs = Builder.CreateFNeg(FAbs);
-      return new BitCastInst(FNegFAbs, I.getType());
-    }
+    Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp);
+    Value *FNegFAbs = Builder.CreateFNeg(FAbs);
+    return new BitCastInst(FNegFAbs, I.getType());
   }
 
   // (X & C1) | C2 -> X & (C1 | C2) iff (X & C2) == C2
@@ -4851,18 +4845,15 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
     // This is generous interpretation of noimplicitfloat, this is not a true
     // floating-point operation.
     //
-    // Assumes any IEEE-represented type has the sign bit in the high bit.
+    // Assumes any floating point type has the sign bit in the high bit.
     // TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
     Value *CastOp;
     if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
-        match(Op1, m_SignMask()) &&
+        CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_SignMask()) &&
         !Builder.GetInsertBlock()->getParent()->hasFnAttribute(
             Attribute::NoImplicitFloat)) {
-      Type *EltTy = CastOp->getType()->getScalarType();
-      if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) {
-        Value *FNeg = Builder.CreateFNeg(CastOp);
-        return new BitCastInst(FNeg, I.getType());
-      }
+      Value *FNeg = Builder.CreateFNeg(CastOp);
+      return new BitCastInst(FNeg, I.getType());
     }
   }
 
diff --git a/llvm/test/Transforms/InstCombine/fabs-as-int.ll b/llvm/test/Transforms/InstCombine/fabs-as-int.ll
index 9d28cae8f04d6..f0e83ca6302fe 100644
--- a/llvm/test/Transforms/InstCombine/fabs-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fabs-as-int.ll
@@ -289,8 +289,8 @@ define i128 @fabs_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
 define i128 @fabs_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
 ; CHECK-LABEL: define i128 @fabs_as_int_ppc_fp128_f128_mask
 ; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT:    [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT:    [[AND:%.*]] = and i128 [[BC]], 170141183460469231731687303715884105727
+; CHECK-NEXT:    [[TMP1:%.*]] = call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 [[X]])
+; CHECK-NEXT:    [[AND:%.*]] = bitcast ppc_fp128 [[TMP1]] to i128
 ; CHECK-NEXT:    ret i128 [[AND]]
 ;
   %bc = bitcast ppc_fp128 %x to i128
diff --git a/llvm/test/Transforms/InstCombine/fneg-as-int.ll b/llvm/test/Transforms/InstCombine/fneg-as-int.ll
index f8d88b4f238f2..590aca687e5b5 100644
--- a/llvm/test/Transforms/InstCombine/fneg-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fneg-as-int.ll
@@ -291,8 +291,8 @@ define i128 @fneg_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
 define i128 @fneg_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
 ; CHECK-LABEL: define i128 @fneg_as_int_ppc_fp128_f128_mask
 ; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT:    [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT:    [[XOR:%.*]] = xor i128 [[BC]], -170141183460469231731687303715884105728
+; CHECK-NEXT:    [[TMP1:%.*]] = fneg ppc_fp128 [[X]]
+; CHECK-NEXT:    [[XOR:%.*]] = bitcast ppc_fp128 [[TMP1]] to i128
 ; CHECK-NEXT:    ret i128 [[XOR]]
 ;
   %bc = bitcast ppc_fp128 %x to i128
diff --git a/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll b/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
index 8b245bdd79299..a0894c3febc94 100644
--- a/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
+++ b/llvm/test/Transforms/InstCombine/fneg-fabs-as-int.ll
@@ -317,8 +317,9 @@ define i128 @fneg_fabs_as_int_ppc_fp128_f64_mask(ppc_fp128 %x) {
 define i128 @fneg_fabs_as_int_ppc_fp128_f128_mask(ppc_fp128 %x) {
 ; CHECK-LABEL: define i128 @fneg_fabs_as_int_ppc_fp128_f128_mask
 ; CHECK-SAME: (ppc_fp128 [[X:%.*]]) {
-; CHECK-NEXT:    [[BC:%.*]] = bitcast ppc_fp128 [[X]] to i128
-; CHECK-NEXT:    [[OR:%.*]] = or i128 [[BC]], -170141183460469231731687303715884105728
+; CHECK-NEXT:    [[TMP1:%.*]] = call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 [[X]])
+; CHECK-NEXT:    [[TMP2:%.*]] = fneg ppc_fp128 [[TMP1]]
+; CHECK-NEXT:    [[OR:%.*]] = bitcast ppc_fp128 [[TMP2]] to i128
 ; CHECK-NEXT:    ret i128 [[OR]]
 ;
   %bc = bitcast ppc_fp128 %x to i128

arsenm · 2025-03-10T08:04:41Z

llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

  // TODO: Unify with APInt matcher. This version allows undef unlike m_APInt
  Value *CastOp;
  if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) &&
-      match(Op1, m_MaxSignedValue()) &&
+      CastOp->getType()->isFPOrFPVectorTy() && match(Op1, m_MaxSignedValue()) &&


It might be worth wrapping this in a predicate with this explicit property

How about adding new matchers like m_IntValue/m_FPValue? They are very useful to work with the bitcast matcher.

@arsenm Do you mean the property "has sign bit in high bit"?

dtcxzyw · 2025-03-11T08:48:15Z

llvm/lib/Support/APFloat.cpp

+                                                  fltNanEncoding::AllOnes,
+                                                  false,
+                                                  false,
+                                                  false};


I don't think so. All the bits are exponent bits (E8M0). It ranges from 2^-127 to 2^127 (255 values). The remaining one is NaN (all ones).

Ooops, it looks like I looked at a different entry, not sure how I ended up there. This one is:

// 8-bit floating point number with (all the) 8 bits for the exponent // like in FP32. There are no zeroes, no infinities, and no denormal values. // This format has unsigned representation only. (U -> Unsigned only). // NaN is represented with all bits set to 1. Bias is 127. // This format represents the scale data type in the MX specification from: // https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf

Okay, that makes sense.

This makes me wonder though whether we need a separate flag. Can we use hasSignedRepr instead, and specify that hasSignedRepr must have the sign bit in the MSB?

IIUC hasSignedRepr is weaker. It just indicates that the semantics doesn't have negative numbers.

llvm/unittests/ADT/APFloatTest.cpp

dtcxzyw · 2025-04-13T16:00:20Z

Ping.

nikic

LGTM

This patch is needed by llvm#130496.

dtcxzyw requested a review from arsenm March 10, 2025 07:39

dtcxzyw requested a review from nikic as a code owner March 10, 2025 07:39

llvmbot added llvm:instcombine llvm:transforms labels Mar 10, 2025

arsenm added the floating-point Floating-point math label Mar 10, 2025

arsenm reviewed Mar 10, 2025

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llvmbot added llvm:support llvm:adt labels Mar 10, 2025

dtcxzyw requested a review from jcranmer-intel March 11, 2025 01:04

dtcxzyw mentioned this pull request Mar 11, 2025

[IR][ADT] Remove APFloat/Type::isIEEE #130496

Merged

nikic reviewed Mar 11, 2025

View reviewed changes

dtcxzyw added 4 commits March 12, 2025 14:12

[InstCombine] Fold fneg/fabs patterns with ppc_f128

616b03c

[ADT] Add hasSignBitInMSB helper

925dfd0

[InstCombine] Reduce changes

fff3484

[InstCombine] Add back comments. NFC.

dde7d59

dtcxzyw force-pushed the remove-is-ieee-pre branch from 29eaf37 to dde7d59 Compare March 12, 2025 06:22

arsenm reviewed Mar 12, 2025

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llvm/unittests/ADT/APFloatTest.cpp Show resolved Hide resolved

[ADT][UnitTest] Test more fp types. NFC.

67b6954

nikic approved these changes Apr 13, 2025

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dtcxzyw merged commit e710a5a into llvm:main Apr 14, 2025
11 checks passed

dtcxzyw deleted the remove-is-ieee-pre branch April 14, 2025 06:30

var-const pushed a commit to ldionne/llvm-project that referenced this pull request Apr 17, 2025

[InstCombine] Fold fneg/fabs patterns with ppc_f128 (llvm#130557)

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This patch is needed by llvm#130496.

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[InstCombine] Fold fneg/fabs patterns with ppc_f128 #130557

[InstCombine] Fold fneg/fabs patterns with ppc_f128 #130557

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[InstCombine] Fold fneg/fabs patterns with ppc_f128 #130557

[InstCombine] Fold fneg/fabs patterns with ppc_f128 #130557

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