CERN Accelerating science

Preprint
Report number	CERN-RD53-PUB-24-002
Title	RD53 Pixel Readout Integrated Circuits for ATLAS and CMS HL-LHC Upgrades
Author(s)	Christiansen, Jorgen (CERN)
Publication	2024
Collaboration	RD53 collaboration
Imprint	2024-05-23
Number of pages	64
Accelerator/Facility, Experiment	RD53
Keywords	RD53 pixel chip ; ATLAS pixel chip ; CMS pixel chip ; Particle tracking detectors (Solid-state detectors) ; Front-end electronics for detector readout ; VLSI circuits ; Radiation-hard electronics
Abstract	The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50x50um$^2$ pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips with different chip sizes to be designed, verified and tested to handle extreme hit rates of 3GHz/cm$^2$ (12GHz per chip) together with significantly increased trigger rate of 1MHz and efficient readout of up to 5.12Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1Grad over 10 years and SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips for the two main CERN experiments. Three generations of pixel chips, and many specific mixed signal building block and radiation test chips, have been submitted and extensively tested to get to final production chips. The large complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.
Submitted by	[email protected]