CERN Accelerating science

ATLAS Note
Report number	ATL-DAQ-PROC-2016-046
Title	The prototype design of gFEX — A component of the L1Calo Trigger for the ATLAS Phase-I upgrade
Author(s)	Chen, Hucheng (Brookhaven Natl. Lab.) ; Begel, Michael (Brookhaven Natl. Lab.) ; Chen, Kai (Brookhaven Natl. Lab.) ; Lanni, Francesco (Brookhaven Natl. Lab.) ; Takai, Helio (Brookhaven Natl. Lab.) ; Tang, Shaochun (Brookhaven Natl. Lab.) ; Wu, Weihao (Brookhaven Natl. Lab.)
Corporate Author(s)	The ATLAS collaboration
Collaboration	ATLAS Collaboration
Publication	2016
Imprint	23 Dec 2016
Number of pages	5
In:	IEEE Nuclear Science Symposium and Medical Imaging Conference, Strasbourg, France, 29 Oct - 6 Nov 2016
DOI	10.1109/NSSMIC.2016.8069899
Subject category	Particle Physics - Experiment
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	The ATLAS experiment will follow the upgrade steps of the Large Hadron Collider (LHC), which will undergo a series of upgrades to increase the luminosity in the next ten years. During the Phase-I upgrade, a new component will be designed for the ATLAS Level-1 calorimeter trigger system to maintain the trigger acceptance against the increasing luminosity - the global feature extractor (gFEX). The gFEX is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W & Z bosons, top quarks and exotic particles in real time at the LHC crossing rate. A prototype v1 with one System-on-Chip Xilinx ZYNQ FPGA, and one Vertex-7 FPGA for technology validation has been designed and tested in 2015. With the lessons learned from the prototype v1, a prototype v2 with three UltraScale FPGAs and one ZYNQ FPGA is implemented on an ATCA module. This board will receive coarse-granularity information from the entire ATLAS calorimeter on 276 optical fibers at the speed up to 12.8 Gb/s synchronous to the 40 MHz LHC clock. The test results of the prototype v2 show that the main gFEX functionalities are working well. Currently it is being used as the test platform for trigger algorithm development and integration with other detector systems. Based on the prototype v2 design, a prototype v3 design, the final prototype before production, has been started. This features a ZYNQ UltraScale+ FPGA and more fiber optical links to provide compatibility for the High-Luiminosity upgrade of the LHC (HL-LHC).
Copyright/License	Preprint: (License: CC-BY-4.0)

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