Author(s)
| Kuhl, A (UC, Santa Cruz) ; Fadeyev, V (UC, Santa Cruz) ; Grillo, A A (UC, Santa Cruz) ; Martinez-McKinney, F (UC, Santa Cruz) ; Nielsen, J (UC, Santa Cruz) ; Spencer, E (UC, Santa Cruz) ; Wilder, M (UC, Santa Cruz) |
Abstract
| The Semi-Conductor Tracker (SCT) in the ATLAS experiment at the Large Hadron Collider (LHC) could be subject to various beam loss scenarios. If a severe beam loss event were to occur, it would be beneficial to know how SCT components would be affected. In the SCT detector modules, a key component is the ABCD application specific integrated circuit (ASIC), the onboard readout electronics of the system. This ASIC has design specifications that it should withstand a 5 nC charge application within 25 ns, which is the period of the LHC bunch crossing. The first test performed is designed to test this limit, reaching a maximum of 10 nC deposited in 25 ns. One model for beam loss predicts that a large charge, of the order of 106 MIPS, could be incident on the detector. According to detector studies, this causes a local field breakdown between the backplane of the sensor, held at 450 V, and the strips. In this case the signal seen on the readout strip has a rise time of about 1 μs due to a charge screening effect. A second test is designed to test this discharge scenario, with a maximum of 90 nC deposited in 1 μs. |