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CERN Document Server 2,039 εγγραφές βρέθηκαν  1 - 10επόμενοτέλος  μετάβαση στην εγγραφή: Η έρευνα πήρε 0.66 δευτερόλεπτα. 
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Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Moreira, Paulo (CERN) ; Kölpin, Alexander (Hamburg, Tech. U.) ; Leroux, Paul (Leuven U.) ; Prinzie, Jeffrey (Leuven U.)
This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to SingleEvent Effects (SEEs) up to 62.5 MeV cm$^{2}$ mg$^{−1}$ as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. [...]
2021 - 16 p. - Published in : Electronics 10 (2021) 2741
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Radiation-tolerant all-digital clock generators for HEP applications / Biereigel, S (CERN ; Geel, Cathol. High Sch. Kempen ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Mendes, E (CERN) ; Hazell, P (CERN) ; Moreira, P (CERN) ; Prinzie, J (Geel, Cathol. High Sch. Kempen)
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. [...]
2023 - 8 p. - Published in : JINST 18 (2023) C01060 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01060
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Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
This article presents a radiation-tolerant digitally controlled complementary metal–oxide–semiconductor (CMOS) ring oscillator design suitable for all-digital phase-locked loop (ADPLL) implementations. To address the challenges presented by harsh radiation environments, a wide tuning range oscillator architecture is presented with superior single-event effect (SEE) tolerance. [...]
2022 - 9 p. - Published in : IEEE Trans. Nucl. Sci. 69 (2022) 17-25 Fulltext: PDF;
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The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis / Leitao, P (CERN) ; Francisco, R (CERN) ; Llopart, X (CERN) ; Tavernier, F (Leuven U.) ; Baron, S (CERN) ; Bonacini, S (CERN) ; Moreira, P (CERN)
A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applications. [...]
2015 - Published in : JINST 10 (2015) C03024 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2014, Aix En Provence, France, 22 - 26 Sep 2014, pp.C03024
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Radiation-Tolerant All-Digital Clock Generators for High Energy Physics / Biereigel, Stefan
The main focus of the presented research is the development and experimental study of radiation-tolerant clock generation circuits intended for applications in high energy physics (HEP) [...]
CERN-THESIS-2022-139 doi:10.26127/BTUOpen-6088. - 215 p.

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The lpGBT PLL and CDR Architecture, Performance and SEE Robustness / Biereigel, Stefan (Brandenburg Tech. U. ; Leuven U. ; CERN) ; Kulis, Szymon (CERN) ; Francisco, Rui (CERN) ; Leitao, Pedro Vicente (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Prinzie, Jeffrey (Leuven U.)
We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. [...]
SISSA, 2020 - 5 p. - Published in : PoS TWEPP2019 (2020) 034 Fulltext: PDF;
In : TWEPP 2019 Topical Workshop on Electronics for Particle Physics, Santiago De Compostela, Spain, 2 - 6 Sep 2019, pp.034
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A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad / Klekotko, A (CERN ; Leuven U.) ; Biereigel, S (CERN) ; Baszczyk, M (CERN) ; Moreira, P (CERN) ; Martina, F (CERN) ; Prinzie, J (Leuven U.) ; Kulis, S (Leuven U.)
This article presents a 25.6-Gbit $\cdot $ s−1 high-speed transmitter (HST) manufactured using 28-nm CMOS technology. The HST macroblock includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100- $\Omega $ line as well as a silicon photonics (SiPh) ring modulator (RM). [...]
2024 - 9 p. - Published in : IEEE Trans. Nucl. Sci. 71 (2024) 2124-2132 Fulltext: PDF;
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Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS / Biereigel, Stefan (CERN ; Leuven U. ; Brandenburg Tech. U.) ; Kulis, Szymon (CERN) ; Leroux, Paul (Leuven U.) ; Moreira, Paulo (CERN) ; Kolpin, Alexander (Hamburg, Tech. U.) ; Prinzie, Jeffrey (Leuven U.)
This article describes a previously unreported single-event radiation effect in spiral inductors manufactured in a commercial CMOS technology when subjected to ionizing radiation. Inductors play a major role as the component determining the frequency of LC tank oscillators, which is why any radiation effect in these passive components can have a detrimental impact on the performance of clock generation circuits. [...]
2021 - 11 p. - Published in : IEEE Trans. Nucl. Sci. 68 (2021) 2587-2597 Fulltext: PDF;
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Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters / Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN) ; Tavernier, F (Leuven U.) ; Prinzie, J (Leuven U.)
Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing thedata rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-ratearchitectures imposes tight constraints on clock signal quality, in particular itsduty-cycle. [...]
2024 - 7 p. - Published in : JINST 19 (2024) C02030 Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02030
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A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS / Biereigel, Stefan (Leuven U.) ; Kulis, Szymon (CERN) ; Leitao, Pedro (CERN) ; Francisco, Rui (CERN) ; Moreira, Paulo (CERN) ; Leroux, Paul (Leuven U.) ; Prinzie, Jeffrey (Leuven U.)
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for high-energy physics and space applications. The CDR employs a novel soft-error tolerant Voltage Controlled Oscillator (VCO) and includes a high-speed feed-forward path, which stabilizes the CDR by compensating for an additional pole introduced in the VCO in order to harden it against ionizing particles. [...]
2019 - 9 p. - Published in : IEEE Trans. Circuits Theor. 67 (2019) 1438-1446
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