CERN Accelerating science

Published Articles
Title	Upgrade of the YARR DAQ system for the ATLAS Phase-II pixel detector readout chip
Author(s)	Whallon, Nikola Lazar (U. Washington, Seattle (main)) ; Heim, Timon (LBNL, Berkeley) ; Garcia-Sciveres, Maurice (LBNL, Berkeley) ; Sautaux, Arnaud (LBNL, Berkeley) ; Oide, Hideyuki (INFN, Genoa) ; Potamianos, Karolos (DESY) ; Hsu, Shih-Chieh (U. Washington, Seattle (main))
Publication	SISSA, 2018
Number of pages	5
In:	PoS TWEPP-17 (2018) 076
In:	Topical Workshop on Electronics for Particle Physics, Santa Cruz, Ca, United States Of America, 11 - 15 Sep 2017, pp.076
DOI	10.22323/1.313.0076
Subject category	Detectors and Experimental Techniques
Accelerator/Facility, Experiment	CERN LHC ; ATLAS
Abstract	Yet Another Rapid Readout (YARR) is a DAQ system based on a software driven architecture using PCIe FPGA boards. It was designed for the readout of current generation ATLAS Pixel detector readout chips, which have a readout bandwidth of 160 Mb/s. YARR has been upgraded to accommodate the higher 5 Gb/s bandwidth of the next generation readout chip in development by the RD53 collaboration for the Phase-II upgrade of the ATLAS and CMS detectors. The performance results of the migration to a new PCIe FPGA board, the PLDA XpressK7, will be presented.
Copyright/License	Copyright owned by the author(s) publication: (License: CC-BY-NC-ND-4.0)

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