Data Paths
CPU has two sections, data section and control section. Data section is also called data paths. Registers, ALU and interconnection bus collectively constitutes a data path. Data paths are of three types:
Single Cycle
Multiple Cycle
Pipeline
Following are some of the important differences between Single Cycle, Multiple Cycle and Pipeline data paths.
| Sr. No. | Key | Single Cycle | Multiple Cycle | Pipeline |
|---|---|---|---|---|
| 1 | Cycle | Single Cycle has one CPI (Clock Cycle Per Instruction). | Multiple Cycle has variable CPIs. | Pipeline has fixed no. of CPIs. |
| 2 | Instruction division | In single cycle, instruction is not divided per CPI. | In multiple cycle, an instruction can be divided in arbitrary steps. | In pipline, an instruction is divided one step per pipeline stage. |
| 3 | Instruction division | In single cycle, one instruction is executed at a time. | In multiple cycle also, one instruction is executed at a time. | In pipline, multiple instructions can be executed at a time. |
| 4 | Extra Registers | In single cycle, extra registers are not needed. | In multiple cycle, extra registers are required. | In pipline also, extra registers are required. |
| 5 | Clock Cycle Time | In single cycle, clock cycle time is long. | In multiple cycle, clock cycle time is short. | In pipline also, clock cycle time is short. |
| 6 | Clock Cycle Overlapping | In single cycle, clock cycle overlapping is not possible. | In multiple cycle, clock cycle overlapping is not present. | In pipline also, clock cycle overlap happens. |