Microcontroller part 9_v1
- 1. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Embedded System PART 9 (I2C) ENG.KEROLES SHENOUDA 1
- 2. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system (I2C) Inter - Integrated Circuit it's time to wake up 2
- 3. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system What is I2C The name stands for “Inter - Integrated Circuit” A Small Area Network connecting ICs and other electronic systems The IIC is also referred to as I2C (I2C) or I square C in many technical literatures. The I2C bus was originally started by Philips, Now It is a widely used standard adapted by many chip making companies I2C is ideal for communication between low-speed devices for a reliable communication over a short distance. Today, a variety of devices are available with I2C Interfaces Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter 3
- 4. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Characteristics Multi Master Multi Slave Synchronous Serial Signal (One wire used for the clock ) Half duplex (One wire use for the data) Also called a 2-wire bus It has only clock and data, with pull –up resistors This reduction of communication pins reduces the package size and power consumption Lines pulled high via resistors 4
- 5. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Line Electrical Characteristics I2C devices use only 2 bidirectional open-drain pins for data communication. To implement I2C, only a 4.7 kilohm pull-up resistor for each of bus lines is needed. This means that if one or more devices pull the line to low (zero) level, the line state is zero and the level of line will be 1 only if none of devices pull the line to low level. At any given moment the I2C bus is: (Idle) state in Master transmit mode or in Master receive mode. 5
- 6. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Characteristics 6
- 7. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Characteristics Two wire serial data & control bus implemented with the serial data (SDA) and clock (SCL) lines Unique start and stop condition Slave selection protocol uses a 7-Bit slave address The bus specification allows an extension to 10 bits Bi-directional data transfer Acknowledgement after each transferred byte. No fixed length of transfer I2C terminology Concepts: Master This is the device that generates clock, starts communication, sends I2C commands and stops communication Slave This is the device that listens to the bus and is addressed by the master Arbitration A process to determine which of the masters on the bus can use it when more masters need to use the bus 7
- 8. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Definitions Master: Initiates a transfer by generating start and stop conditions Generates the clock Transmits the slave address Determines data transfer direction Slave: Responds only when addressed Timing is controlled by the clock line 8
- 9. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Start and Stop Conditions each transmission is initiated by a START condition and is terminated by a STOP condition. the START and STOP conditions are generated by the master. START and STOP conditions are generated by keeping the level of the SCL line high and then changing the level of the SDA line The START condition is generated by a high-to-low change in the SDA line when SCL is high. The STOP condition is generated by a low-to-high (ideal case) change in the SDA line when SCL is high 9 Start Condition Stop Condition SCL SCL SDASDA
- 10. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system How I2C work ? 10
- 11. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 11 Each slave device on the bus should have a unique 7-bit address (we assume the addressing here is 7-bit) Each master must generate its own clock signal and the data can change only when the clock is low. the clock is in the high state until the first master pulls it low. The 7-bit address lets the master address a maximum of 128 slaves on the bus.
- 12. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 12 1. Master_01 sends start condition (S) and controls the clock signal (by set the SCL high and set SDA low) S S S SS S
- 13. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 13 2. Master_01 send a unique 7 bit slave device address (in this example we assume the I2C address is 7 bit) For example slave address = 0x34 (slave_01) S Slave address Slave address Slave address Slave address Slave address Slave address
- 14. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 14 3. Master_01 sends read/write bit (R/W) -0 means W (slave receive) - 1 means R (slave transmit) S Slave address R/W R/W R/W R/W R/WR/W We assume in this example that the master will send the ‘W’ to the Slave
- 15. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 15 4. Slave_01 sends acknowledge bit (ACK) The other Slaves will discard any bytes come through the I2C Bus until the master release the BUS by send (Stop Condition) S Slave address R/W Slave devices that need some time to process received byte or are not ready yet to send the next byte, can pull the clock low to signal to the master that it should wait ACK ACK ACK
- 16. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 16 5. Transmitter (slave or master) transmits 1 byte of data S Slave address R/W ACK Data We assume in this example that the master will send the DATA to the Slave Data Data
- 17. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 17 6. Receiver issues an ACK bit for the byte received S Slave address R/W ACK Data ACK ACK ACK
- 18. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 18 6. Repeat 5 and 6 if more bytes need to be transmitted. S Slave address R/W ACK Data ACK ACK ACK Data ACK Data Data
- 19. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 19 7. If master transmitting, master issues stop condition (P) after last byte of data else master receiving, last byte is not acknowledged by master then the master issues stop condition (P) S Slave address R/W ACK Data ACK Data ACK P P P P P P Now the master_01 Released the BUS
- 20. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 20 7. If master transmitting, master issues stop condition (P) after last byte of data else master receiving, last byte is not acknowledged by master then the master issues stop condition (P) S Slave address R/W ACK Data ACK Data ACK P P P P P P Now the master_01 Released the BUS
- 21. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 21 Master Read from Slave Master Write To Slave
- 23. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK 23
- 24. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK 24 Master Send ACK to slave: 1. Slave transmits last bit 2. Slave will release the SDA line: line will go high 3. Master will pull the SDA line low 4. Master will put a clock pulse on the SCL line 5. Master will release the SDA line. 6. Slave will now regain control of the SDA line Note: An Acknowledge of a byte received by a slave is always necessary, except on the last byte received.
- 25. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK No acknowledge incase (Master Send data to the Slave) If, after transmission of the 8th bit from the master to the slave, the slave does not pull the SDA line low, then this is considered a No ACK condition 25 What is the reason ?
- 26. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK No acknowledge incase (Master Send data to the Slave) If, after transmission of the 8th bit from the master to the slave, the slave does not pull the SDA line low, then this is considered a No ACK condition 26 What is the reason ? Maybe: The slave is not longer there The slave is not longer there
- 27. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK No acknowledge incase (Master Send data to the Slave) If, after transmission of the 8th bit from the master to the slave, the slave does not pull the SDA line low, then this is considered a No ACK condition 27 What is the reason ? Maybe: -The slave is not longer there. -The slave missed a pulse and got out of sync with the SCL line of the master
- 28. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK No acknowledge incase (Master Send data to the Slave) If, after transmission of the 8th bit from the master to the slave, the slave does not pull the SDA line low, then this is considered a No ACK condition 28 What is the reason ? Maybe: -The slave is not longer there. -The slave missed a pulse and got out of sync with the SCL line of the master. -The bus is "stuck". One of the lines could be held low permanently.
- 29. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK No acknowledge incase (Master Send data to the Slave) If, after transmission of the 8th bit from the master to the slave, the slave does not pull the SDA line low, then this is considered a No ACK condition 29 What is the reason ? Maybe: -The slave is not longer there. -The slave missed a pulse and got out of sync with the SCL line of the master. -The bus is "stuck". One of the lines could be held low permanently. P P P PP Then Master should abort by attempting to send a stop condition on the bus.
- 30. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C: ACK, NACK, No ACK 30 Not acknowledge (NACK) - after a master has read a byte from a slave That happen If the master wants to stop receiving data from the slave, it will not send ACK and then it must be able to send a stop condition
- 32. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system What happen if two masters initiate start condition at the same time or have multiple slave devices that respond to a single address? 32
- 33. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Arbitration I2C protocol supports a multi-master bus system. This doesn't mean that more than one master can use the bus at the same time. Rather, each master waits for the current transmission to finish and then starts to use the bus. But it is possible that two or more masters initiate a transmission at about the same time (a bus collision might occur). In this case the arbitration happens. is done by having each device that may be trying to use the data line place their bit of data as they normally would (driving SDA low or leaving it to idle high) and then reading the voltage level on the line to see if it is what the device expects. 33
- 34. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Arbitration The Arbitration is done by having each device that may be trying to use the data line place their bit of data as they normally would (driving SDA low or leaving it to idle high) and then reading the voltage level on the line to see if it is what the device expects. If a device sees that the line has been driven low when it expects it to be idling high, it will conclude that another device must also be using the SDA line and losing arbitration and wait for a stop condition before attempting to transmit its message again. 34
- 35. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Arbitration The second device, seeing that the voltage level is as it expected, will continue transmitting its message although it will also continue to check the line after each bit in case there is another device that has happened to exactly match its bit values 35
- 36. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Arbitration(another example) 36
- 37. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Arbitration(another example) 37
- 38. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Arbitration(another example) 38
- 39. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Bus Arbitration(another example) 39 The moment their data bits do not match any more then The Master 2 loses arbitration and It must backs Off because when Master 2 tries to move the SDA line high the data on the bus remains low (Master 1 already occupies it)
- 40. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Multibyte burst write/read 40
- 41. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Multibyte burst write Burst mode writing is an effective means of loading consecutive locations In burst mode, we provide the address of the first location, followed by the data for that location. From then on, consecutive bytes are written to consecutive memory locations. 1. Generate a START condition. 2. Transmit the slave address followed by zero (for write). 3. Transmit the address of the first location. 4. Transmit the data for the first location and from then on, simply provide consecutive bytes of data to be placed in consecutive memory locations. 5. Generate a STOP condition. 41
- 42. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Multibyte burst read Burst mode reading is an effective way of bringing out the contents of consecutive locations. In burst mode, we provide the address of the first location only 1. Generate a START condition 2. Transmit the slave address followed by zero (for address write). 3. Transmit the address of the first location. 4. Generate a START (REPEATED START) condition. 5. Transmit the slave address followed by one (for read). 6. Read the data from the first location and from then on, bring contents out from consecutive memory locations. 7. Generate a STOP condition. 42
- 43. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI - Two-wire Serial Interface (I2C) in ATMEGA(32) 43
- 45. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Features only two Bus Lines Needed Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7-bit Address Space Allows up to 128 Different Slave Addresses Multi-master Arbitration Support Fully Programmable Slave Address 45
- 46. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemTWI (I2C) Module 46 The bit rate generation unit controls the frequency of the system clock (SCL) when operating in a master mode
- 47. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemTWI (I2C) Module 47 The bus interface unit detects and generates START, REPEATED START and STOP conditions. It also detects arbitration, controls sending or receiving ACK, and also transfers packets of data or address.
- 48. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemTWI (I2C) Module 48 The address match unit compares the received address byte with the 7-bit address in TWI address register and informs the control unit upon an address match.
- 49. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemTWI (I2C) Module 49 The control unit controls the TWI module and generates responses according to settings in the TWI control register. It also sets the contents of the status register according to current state.
- 50. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI (I2C) in atmega32 In the AVR microcontroller, five major registers are associated with the TWI. They are: 1. TWBR (TWI Bit rate Register) 2. TWCR (TWI Control Register) 3. TWSR (TWI Status Register) 4. TWAR (TWI Address Register) 5. TWDR (TWI Data Register) 50
- 51. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWBR – TWI Bit Rate Register 51
- 52. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI Control Register (TWCR) 52 Bit 7 - TWINT: TWI Interrupt This bit is set by hardware when the TWI module has finished its current job. If the TWI and general interrupt are enabled, changing TWINT to one will cause the MCU to jump to the TWI interrupt vector. Clearing this flag starts the operation of the TWI. TWINT must be cleared by software.
- 53. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system More Details Bit 7 - TWINT: TWI Interrupt When the TWI hardware finishes its job, it sets the TWINT bit to one. If the TWI and general interrupts are enabled, changing TWINT to HIGH will cause the MCU to jump to the TWI interrupt vector. When the TWINT bit is set, the TWI module "stretches" the SCL line to provide enough time for software to do specified jobs. When the software finishes its job, it must clear the TWINT bit to resume the operation of the TWI module. Notice that all accesses to the TWI address, status, and data registers must be complete before clearing this flag. If you try to write to the TWI Data Register when TWINT is low, a collision will happen and the TWI collision flag (TWWC) will be set to HIGH by hardware. Software can monitor (poll) the TWI bit to know when the TWI module finishes its job and is ready for a new command. 53
- 54. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 54 Bit 7 - TWINT: TWI Interrupt
- 55. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI Control Register (TWCR) 55 Bit 6 - TWEA: TWI Enable Acknowledge Making this bit HIGH will enable the generation of ACK when needed in slave or receiver mode
- 56. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system More Details Bit 6 - TWEA: TWI Enable Acknowledge Making this bit HIGH will enable the generation of the ACK bit if any of the following conditions are met: 1. The TWI Address Match module detects that the TWI module is addressed by receiving its own slave address from the bus. 2. A general call has been received while the TWGCE bit in the TWAR is set to one (to enable accepting of global calls). 3. A data byte has been received in each of the receiving modes, master receiver or slave receiver mode. If you clear the TWEA bit to zero, the device will not generate ACK and will be virtually disconnected from the TWI bus. 56
- 57. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI Control Register (TWCR) 57 Bit 5 - TWSTA: TWI START condition Bit Making this bit HIGH will generate a START condition if the bus is free; otherwise, the TWI module waits for the bus to become free and then generates a START condition
- 58. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI Control Register (TWCR) 58 Bit 4 - TWSTO: TWI STOP condition bit In master mode, making this bit HIGH causes the TWI to generate a STOP condition. This bit is cleared by hardware when the STOP condition is transmitted. Bit 3 - TWWC: TWI Write Collision Flag This bit is set HIGH when we attempt to access the TWI Data Register when TWINT is low. This flag is cleared by writing to the TWDR register when TWINT is high.
- 59. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWI Control Register (TWCR) 59 Bit 2 - TWEN: TWI Enable Making this bit HIGH enables the TWI module. Bit 0 - TWIE: TWI Interrupt Enable Making this bit HIGH enables the TWI interrupt if the general interrupt is enabled.
- 60. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWSR – TWI Status Register 60
- 61. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWDR – TWI Data Register 61
- 62. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system TWAR – TWI (Slave) Address Register 62 TWAR contains the 7-bit slave address to which the TWI will respond when working as slave. The eighth bit (LSB) of TWAR is TWGCE (TWI General Call Recognition Enable). It controls recognition of general call address (000 0000). If this bit is set to one, receiving of a general call address will cause an interrupt request.
- 64. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Transmission Modes 64 The TWI can operate in one of four major modes: • Master Transmitter (MT) • Master Receiver (MR) • Slave Transmitter (ST) • Slave Receiver (SR)
- 65. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Status Codes for Master Transmitter Mode 65
- 66. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 66 Formats and States in the Master Transmitter Mode
- 67. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemStatus codes for Master Receiver Mode 67
- 68. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Formats and States in the Master Receiver Mode 68
- 69. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Status Codes for Slave Receiver Mode 69
- 71. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Status Codes for Slave Transmitter Mode 71
- 73. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Lab1: Master Transmitter Slave Receiver 73
- 74. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Lab1: Master Transmitter Slave Receiver 74
- 75. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Lab1: Master Transmitter Slave Receiver 75
- 78. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system I2C Lab2: Master Receiver Slave Transmitter 78
- 84. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system HOW TO SELECT Between I2C and SPI 84 In your opinion
- 85. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Selecting Between I2C and SPI the two main serial communication protocols, requires a good understanding of the advantages and limitations of I2C, SPI, and your application I2C requires only two wires, while SPI requires three or four SPI supports higher speed full-duplex communication while I2C is slower I2C supports multiple devices on the same bus without additional select signal lines through in-communication device addressing while SPI requires additional signal lines to manage multiple devices on the same bus I2C ensures that data sent is received by the slave device while SPI does not verify that data is received correctly I2C can be locked up by one device that fails to release the communication bus I2C is cheaper to implement than the SPI communication protocol SPI only supports one master device on the bus while I2C supports multiple master devices 85
- 86. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 86 Features UART SPI I2C Full Form Universal Asynchronous Receiver/Transmitter Serial Peripheral Interface Inter-Integrated Circuit Interface Diagram Pin Designations TxD: Transmit Data RxD: Receive Data SCLK: Serial Clock MOSI: Master Output, Slave Input MISO: Master Input, Slave Output SS: Slave Select SDA: Serial Data SCL: Serial Clock
- 87. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 87 Features UART SPI I2C Data rate As this is is asynchronous communication, data rate between two devices wanting to communicate should be set to equal value. Maximum data rate supported is about 230 Kbps to 460kbps. Maximum data rate limit is not specified in SPI interface. Usually supports about 10 Mbps to 20 Mbps I2C supports 100 kbps, 400 kbps, 3.4 Mbps. Some variants also supports 10 Kbps and 1 Mbps. Distance Lower about 50 feet highest Higher Type of communication Asynchronous Synchronous Synchronous
- 88. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 88 Features UART SPI I2C Number of masters Not Application One One or more than One Clock No Common Clock signal is used. Both the devices will use there independent clocks. There is one common serial clock signal between master and slave devices. There is common clock signal between multiple masters and multiple slaves. Hardware complexity lesser less more Protocol For 8 bits of data one start bit and one stop bit is used. Each company or manufacturers have got their own specific protocols to communicate with peripherals. Hence one needs to read datasheet to know read/write protocol for SPI communication to be established. For example we would like SPI communication between microcontroller and EPROM. Here one need to go through read/write operational diagram in the EPROM data sheet. It uses start and stop bits. It uses ACK bit for each 8 bits of data which indicates whether data has been received or not. Figure depicts the data communication protocol.
- 89. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 89 Features UART SPI I2C Software addressing As this is one to one connection between two devices, addressing is not needed. Slave select lines are used to address any particular slave connected with the master. There will be 'n' slave select lines on master device for 'n' slaves. There will be multiple slaves and multiple masters and all masters can communicate with all the slaves. Upto 27 slave devices can be connected/addressed in the I2C interface circuit. Advantages • It is simple communication and most popular which is available due to UART support in almost all the devices with 9 pin connector. It is also referred as RS232 interface. •It is simple protocol and hence so not require processing overheads. •Supports full duplex communication. •Due to separate use of CS lines, same kind of multiple chips can be used in the circuit design. •SPI uses push-pull and hence higher data rates and longer ranges are possible. •SPI uses less power compare to I2C •Due to open collector design, limited slew rates can be achieved. •More than one masters can be used in the electronic circuit design. •Needs fewer i.e. only 2 wires for communication. •I2C addressing is simple which does not require any CS lines used in SPI and it is easy to add extra devices on the bus. •It uses open collector bus concept. Hence there is bus voltage flexibity on the interface bus. •Uses flow control.
- 90. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 90 Features UART SPI I2C Disadvantages • They are suitable for communication between only two devices. • It supports fixed data rate agreed upon between devices initially before communication otherwise data will be garbled. • As number of slave increases, number of CS lines increases, this results in hardware complexity as number of pins required will increase. • To add a device in SPI requires one to add extra CS line and changes in software for particular device addressing is concerned. •Master and slave relationship can not be changed as usually done in I2C interface. •No flow control available in SPI. •Increases complexity of the circuit when number of slaves and masters increases. •I2C interface is half duplex. •Requires software stack to control the protocol and hence it needs some processing overheads on microcontroller/microprocessor .
- 91. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system References https://www.newbiehack.com/MicrocontrollersABeginnersGuideIntroductionandInterfacinganLCD.aspx http://www.slideshare.net/MathivananNatarajan/asynchronous-serial-data-communication-and-standards https://www.slideshare.net/AnkitSingh13/uart-32550652 the avr microcontroller and embedded. System using assembly and c. Muhammad Ali Mazidi Embedded Systems lectures “Engr. Rashid Farid Chishti” https://www.corelis.com/education/SPI_Tutorial.htm http://ftm.futureelectronics.com/2014/09/nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster-alternative-to- standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems/ http://www.byteparadigm.com/products/spi-storm/spi-storm-advanced-information/ https://stackoverflow.com/questions/17125505/what-makes-a-better-constant-in-c-a-macro-or-an-enum https://blog.digilentinc.com/i2c-how-does-it-work/#prettyPhoto https://rophoenixmakerevolution.files.wordpress.com/2015/09/spi-and-can-bus.pdf http://denethor.wlu.ca/cp316/lectures/Serial_Interconnect_Bus.pdf 91