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QUAD SPI [QSPI]
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QUAD SPI [QSPI]
Multi I/O variants such as dual I/O and quad
I/O add additional data lines to the standard
for increased throughput. This
performance increase enables random
access and direct program execution from
flash memory (execute-in-place)
A multi I/O SPI device is capable of
supporting increased bandwidth or
throughput from a single device. A dual
I/O (two-bit data bus) interface enables
transfer rates to double compared to the
standard serial Flash memory devices.
A quad I/O (four-bit data bus) interface
improves throughput four times.
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SPCR – SPI Control Register
Bits 1:0 – SPRn: SPI Clock Rate Select [n = 1:0]
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Lab1 : transmit a
character between
two ATmega32
microcontrollers
[Solution] (Master)
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Lab1 : transmit a
character between
two ATmega32
microcontrollers
[Solution] (Slave)
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Microcontroller part 8_v1
- 1. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Embedded System PART 8 (SPI) ENG.KEROLES SHENOUDA 1
- 2. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system (SPI) Serial Peripheral Interface it's time to wake up 2
- 3. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI (Serial Peripheral Interface) synchronous data transfer Full-duplex Single Master / multi slave Serial interface Multiple slave devices are supported through selection with individual slave select (SS) lines The SPI bus was originally started by Motorola Corp. (now Freescale), but in recent years has become a widely used standard adapted by many semiconductor chip companies It can be used to communicate with a serial peripheral device like external EEPROM or with another microcontroller with an SPI interface 3
- 4. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Advantages of SPI Higher throughput (Faster) SPI: 10Mbs – 20Mbs Simple Receiver Hardware >>> Simple Shift Register Support Multiple Slaves Lower power Requirements than I2C. 4
- 5. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Disadvantages of SPI Requires more Pins Master must control all communications (Slave doesn’t issue the transaction). Separate SS Lines. No Flow Control (must know slave speed) 5
- 6. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI BUS Protocol These 4 pins, SDI, SDO, SCLK, and CE, make the SPI a 4- wire interface. The SDI, SDO, SCLK, and CE signals are alternatively named as MOSI, MISO, SCK, and SS. 6
- 7. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Interface The SPI bus specifies four logic signals: • SCLK(SCK,CLK) : Serial Clock (output from master). • MOSI(SIMO,SDI,DI) : Master Output, Slave Input (output from master). • MISO(SIMO,SDO,DO) : Master Input, Slave Output (output from slave). • SS (CS,CE,CEN): Slave Select (active low, output from master). 7
- 8. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Master Slave Setup In this setup, there are 3 slave devices. The SDO lines are tied together to the SDI line of the master. The master determines which chip it is talking to by the CS lines. For the slaves that are not being talked to, the data output goes to a Hi Z state Multiple Independent Slave Configuration 8
- 9. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system How SPI works ? 9
- 10. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system How SPI works ? SPI consists of two shift registers, one in the master and the other in the slave side. Also, there is a clock generator in the master side that generates the clock for the shift registers. 10
- 11. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system HOW SPI WORKS? The serial-out pin of the master shift register is connected to the serial-in pin of the slave shift register by MOSI (Master Out Slave In). The serial-in pin of the master shift register is connected to the serial-out pin of the slave shift register by MISO (Master In Slave Out). The master clock generator provides clock to the shift registers in both the master and slave. The clock input of the shift registers can be falling- or rising-edge triggered. Shift registers are 8 bits long. So after 8 clock pulses, the contents of the two shift registers are interchanged. When the master wants to send a byte of data, it places the byte in its shift register and generates 8 clock pulses. 11
- 12. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system HOW SPI WORKS? After 8 clock pulses the byte is transmitted to the other shift register. When the master wants to receive a byte of data, the slave side should place the byte in its shift register, and after 8 clock pulses the data will be received by the master shift register. It must be noted that SPI is full duplex, meaning that it sends and receives data at the same time. 12
- 13. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemSPI ” Serial Peripheral Interface ” How SPI works ? Master Slave 13
- 14. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemSPI ” Serial Peripheral Interface ” How SPI works ? Master Slave 14
- 15. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Data Transfer in SPI M0 M1 M2 M3 M4 M5 M6 M7 S0 S1 S2 S3 S4 S5 S6 S7 MASTER SLAVE MOSI MISO 15
- 16. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Data Transfer in SPI M1 M2 M3 M4 M5 M6 M7 S0 S1 S2 S3 S4 S5 S6 S7 M0 MASTER SLAVE MOSI MISO 16
- 17. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Data Transfer in SPI M2 M3 M4 M5 M6 M7 S0 S1 S2 S3 S4 S5 S6 S7 M0 M1 MASTER SLAVE MOSI MISO 17
- 18. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Data Transfer in SPI S0 S1 S2 S3 S4 S5 S6 S7 M0 M1 M2 M3 M4 M5 M6 M7 MASTER SLAVE MOSI MISO 18
- 19. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Draw this Setup “SPI Master Slave Setup with Multiple slave cascaded” good question 19
- 20. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Master Slave Setup Multiple slave cascaded In this example, each slave is cascaded so that the output of one slave is the input of another. When cascading, they are treated as one slave and connecting to the same chip select 20
- 21. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI With Flash Memories (custom protocol) 21
- 22. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Simple SPI Write Transaction Most SPI flash memories have a write status register command that writes one or two bytes of data. To write to the status register, the SPI host first enables the slave select line for the current device. The master then outputs the appropriate instruction followed by two data bytes that define the intended status register contents. Since the transaction does not need to return any data, the slave device keeps the MISO line in a high impedance state and the master masks any incoming data. Finally, slave select is de-asserted to complete the transaction. 22
- 23. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Simple SPI Read Transaction A status register read transaction would be similar to the write transaction, but now takes advantage of data returned from the slave. After sending the read status register instruction, the slave begins transmitting data on the MISO line at a rate of one byte per eight clock cycles. The host receives the bitstream and completes the transaction by de-asserting SS# 23
- 24. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Which type of SPI act as “half duplex” serial communication ? good question 24
- 25. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Bus 3-Wire 25
- 26. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Bus 3-Wire and Multi-IO Configurations There is also a widely used standard called a 3-wire interface bus. In a 3-wire interface bus, we have SCLK and CE, and only a single pin for data transfer. The SPI 4-wire bus can become a 3-wire interface when the SDI and SDO data pins are tied together. But there are some major differences between the SPI and 3-wire devices in the data transfer protocol. For that reason, a device must support the 3-wire protocol internally in order to be used as a 3-wire device. Many devices such as the DS1306 RTC (real-time clock) support both SPI and 3-wire protocols. 26
- 27. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Bus 3-Wire and Multi-IO Configurations In 3-wire mode, MOSI and MISO lines are combined to a single bidirectional data Transactions are half-duplex to allow for bidirectional communication. Reducing the number of data lines and operating in half-duplexmode also decreases maximum possible throughput 27
- 28. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system QUAD SPI [QSPI] 28
- 29. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system QUAD SPI [QSPI] Multi I/O variants such as dual I/O and quad I/O add additional data lines to the standard for increased throughput. This performance increase enables random access and direct program execution from flash memory (execute-in-place) A multi I/O SPI device is capable of supporting increased bandwidth or throughput from a single device. A dual I/O (two-bit data bus) interface enables transfer rates to double compared to the standard serial Flash memory devices. A quad I/O (four-bit data bus) interface improves throughput four times. 29
- 30. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Example: QSPI connected to Spansion Flash 30
- 31. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Example: Quad mode fast read sequence for Spansion S25FL016K or equivalent Quad IO is gaining popularity with flash memories for its increased performance. Instead of using a single output and single input interface, Quad IO utilizes 4 separate half- duplex data lines for both transmitting and receiving data for up to four times the performance of standard 4-wire SPI. 31
- 32. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Example: Quad mode fast read sequence for Spansion S25FL016K or equivalent This example read command for a Spansion S25FL016K serial NOR flash device. To read from the device, a fast read command (EBh) is first sent by the master on the first IO line while all others are tristated. Next, the host sends the address; since the interface now has 4 bidirectional data lines, it can utilize these to send a complete 24-bit address along with 8 mode bits in just 8 clock cycles. The address is then followed with 2 dummy bytes (4 clock cycles) to allow the device additional time to set up the initial address. 32
- 34. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system 8-bit standard SPI access •SPI (Serial Peripheral Interface): 4 wires protocols using MOSI, MISO, SCLK and SS. 34
- 35. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI-3 variant of the SPI protocol where MOSI and MISO are merged as a single bi-directional data line, with bus turn-around phases. 35
- 36. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Dual-SPI variant of the SPI protocol that includes modes in which 2 data lines are used for conveying data. 36
- 37. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Quad-SPI variant of the SPI protocol that includes modes in which 4 data lines are used for conveying data. 37
- 38. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI ON atmega32 38
- 39. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Block Diagram 39
- 40. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Master-slave Interconnection 40
- 41. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Pin Overrides 41
- 42. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SS Pin Functionality 42
- 43. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SS Pin Functionality 43
- 44. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI on Atmega32 Register Descriptions The AVR contains the following three registers that deal with SPI: SPCR – SPI Control Register – This register is basically the master register i.e. it contains the bits to initialize SPI and control it. SPSR – SPI Status Register – This is the status register. This register is used to read the status of the bus lines. SPDR – SPI Data Register – The SPI Data Register is the read/write register where the actual data transfer takes place. 44
- 45. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPCR – SPI Control Register Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set. Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. 45
- 46. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPCR – SPI Control Register Bit 3 – CPOL: Clock Polarity Bit 2 – CPHA: Clock Phase 46
- 47. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPCR – SPI Control Register Bits 1:0 – SPRn: SPI Clock Rate Select [n = 1:0] 47
- 48. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPSR – SPI Status Register Bit 7 – SPIF: SPI Interrupt Flag 1. When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. 2. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR) 48
- 49. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPSR – SPI Status Register Bit 6 – WCOL: Write Collision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. 49
- 50. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPSR – SPI Status Register Bit 0 – SPI2X: Double SPI Speed Bit 50
- 51. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemSPDR – SPI Data Register is a read/write register The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. • SPID7 is MSB • SPID0 is LSB 51
- 52. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence Before you start data transmission, you should set SPI Mode (Clock Polarity and Clock Phase) by setting the values of the CPOL and CPHA bits in SPCR. You can operate in either master or slave modes. Master operating mode If you want to work in master mode, you should set the MSTR bit to one. Also you should set SCK frequency by setting the values of SPI2X, SPR1, and SPR2. Then you should enable SPI by setting the SPIE bit to one before you start data transmission. Writing a byte to the SPI Data Register (SPDR) starts data exchange by starting the SPI clock generator. After shifting the last (8th) bit, the SPI clock generator stops and the SPIF flag changes to one. 52
- 53. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence The byte in the master shift register and the byte in the slave shift register are exchanged after the last clock. Notice that you cannot write to the SPI Data Register before transmission is completed, otherwise the collision happens. To get the received data you should read it from SPDR before the next byte arrives. We can use interrupts or poll the SPIF to know when a byte is exchanged. 53
- 54. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Master Mode # define F_CPU 1000000UL // define crystal frequency for delay.h #include <avr/io.h> // standard AVR header #include <util/delay.h> #define SS 4 // Slave Select is Bit No.4 #define MOSI 5 // Master Out Slave In is Bit No.5 #define MISO 6 // Master In Slave Out is Bit No.6 #define SCK 7 // Shift Clock is Bit No.7 void SPI_MasterInit(void){ // Set MOSI, SCK and SS as Output Pins DDRB |= (1<<MOSI) | (1<<SCK) | (1<<SS) ; DDRB &= ~(1<<MISO); // Set MISO as an Input Pin // Enable SPI, Master mode, Shift Clock = CLK /16 SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } 54
- 55. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Master Mode unsigned char SPI_MasterTransmit(unsigned char cData){ SPDR = cData; // Start transmission while(!(SPSR & (1<<SPIF))); // Wait for transmission complete return SPDR; // return the received data } 55
- 56. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Initialize SPI Master Device (with SPI interrupt) // Initialize SPI Master Device (with SPI interrupt) void spi_init_master (void) { // Set MOSI, SCK as Output DDRB=(1<<5)|(1<<3); // Enable SPI, Set as Master // Prescaler: Fosc/16, Enable Interrupts //The MOSI, SCK pins are as per ATMega8 SPCR=(1<<SPE)|(1<<MSTR)|(1<<SPR0)|(1<<SPIE); // Enable Global Interrupts sei(); } 56
- 57. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Slave Mode Slave Operating Mode When AVR is configured as a slave, the function of the SPI interface depends on the SS pin. If the SS is driven high, MISO is tri-stated and the SPI interface sleeps. Only the contents of SPDR may be updated in this state. When SS is driven low, the data will be shifted by incoming clock pulses on the SCK pin. SPIF changes to one when the last bit of a byte has been shifted completely. Notice that the slave can place new data to be sent into SPDR before reading the incoming data; this is because in AVR there are two one-byte buffers to store received data 57
- 58. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Slave Mode In slave mode there is no need to set SCK frequency because the SCK is generated by the master. But you must select the SPI mode (Clock Phase and Clock Polarity) and Data Order to match with SPI mode and Data Order of the other side (master device). Finally you should enable the SPI by setting the SPIE bit of SPCR to one. 58
- 59. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Slave Mode #define F_CPU 1000000UL // define crystal frequency for delay.h #include <avr/io.h> // standard AVR header #include <util/delay.h> #define SS 4 // Slave Select is Bit No.4 #define MOSI 5 // Master Out Slave In is Bit No.5 #define MISO 6 // Master In Slave Out is Bit No.6 #define SCK 7 // Shift Clock is Bit No.7 void SPI_SlaveInit(void){ DDRB |= (1<<MISO); // Set MISO as an Output Pin // Set MOSI, SCK and SS as Input Pins DDRB &= ~(1<<MOSI) & ~(1<<SCK) & ~(1<<SS) ; // Enable SPI as a Slave Device SPCR = (1<<SPE); } 59
- 60. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Code Sequence on Slave Mode unsigned char SPI_SlaveReceive(unsigned char cData){ SPDR = cData; // send cData to master // Wait for reception complete while(!(SPSR & (1<<SPIF))); // Return received data return SPDR; } 60
- 61. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab 1 First Clock Edge LSB goes at end 61
- 62. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 62
- 63. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers master slave Master send Ascending Counter value Slave send descending Counter value 63
- 64. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 64
- 65. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 65
- 66. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 66
- 67. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 67
- 68. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 68
- 69. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers 69
- 70. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers [Solution] (Master) 70
- 71. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab1 : transmit a character between two ATmega32 microcontrollers [Solution] (Slave) 71
- 72. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemMAX7221 Interfacing and Prog… 7-Segment Display: In many applications, when you want to display numbers, 7-segments are the best choice. These displays are made of 7 LEDs to show different numbers plus another LED to display the decimal point. 72
- 73. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 Interfacing and Prog… If you want to connect four 7-segment LEDs directly to a microcontroller you need 4 x 8 = 32 pins. This is not feasible. The MAX7221 IC is supports up to eight 7-segment LEDs. We can connect the MAX7221 to the AVR chip using SPI protocol and control up to eight 7-segment LEDs. The MAX7221 contains an internal decoder that can be used to convert binary numbers to 7-segment codes. That means we do not need to refresh the 7-segment LEDs. All you need to do is to send a binary number to the MAX7221, and the chip decodes the binary data and displays the number. The device includes analog and digital brightness control, an 8x8 static RAM that stores each digit, and a test mode that forces all LEDs on. 73
- 74. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 Pins and Connections The MAX7221 is a 24-pin DIP chip. It can be directly connected to the AVR and con-trol up to eight 7-segment LEDs. A resistor or a potentiometer is the only external component that you need. Next, we will discuss the pins of the MAX7221. GND: Pin 4 and pin 9 are the ground. These should be connected to system ground Vcc: Pin 19 is the VCC and should be connected to the +5V.this pin is also the power to drive the 7- segments and the connecting wire to this pin should be able to handle 100-300 mA. 74
- 75. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 Pins and Connections ISET: Pin 18 is ISET and sets the maximum segment current. This pin should be connected to VCC through a resistor. A 10KΩ resistor can be connected to this pin. If you want to manually control the intensity of the segments' light, you can replace the resistor with a 50KΩ potentiometer. CS :Pin 12 is the chip select pin and should be connected to the SS pin of the AVR. Serial data is loaded into the chip while CS is low, and the last 16 bits of the serial data are latched on CS's rising edge. 75
- 76. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 Pins and Connections DIN: Pin 1 is the serial data input and should be connected to the MOSI pin of the AVR. On CLK's rising edge, data on this pin is loaded into the internal shift register. Notice that the MAX7221 uses the SPI Mode 0, that is, read on rising edge and change on falling edge.. CLK: Pin 13 is the serial clock input and should be connected to the SCK pin of the AVR. On MAX7221 the clock input is inactive when CS is high. DOUT: Pin 24 is the serial data output and is used to connect more than one MAX7221 to a single SPI bus. 76
- 77. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 Pins and Connections DIG0-DIG7: The DIG pins are the 7-segment selector pins and should be connected to the 7-segments' common cathode pin. The MAX7221 chip can control up to eight 7-segment LEDs. These eight 7-segment dispalys are designated as DIGO to DIG7. SEGA…SEGG and DP: These pins select each segment and should be connected to segments of each 7- segment accordingly. 77
- 78. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 data packet format In MAX7221, data packets are 16 bits long (two bytes). You should first make CS low before transmitting; then you transmit two bytes of data and terminate the transmission by making CS high. The first byte (MSBs) of each packet contains the command control bits, and the second byte is the data to be displayed. The upper four bits (D15-D12) of the command byte are don't care and the lower four bits (D11-D8) are used to identify the meaning of the data byte to be followed. The second byte (D7-D0) of the two-byte packet is called the data byte and is the actual data to be displayed or control the 7-segment driver. Table 17-3 shows the binary and hex values of each command. 78
- 79. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 data packet format 79
- 80. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system MAX7221 data packet format 80
- 82. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab2: Use MAX7221 to send a sequence Number to Three 7-segment 82
- 83. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab2: Use MAX7221 to send a sequence Number to eight 7-segment SPI Master will increment counter And display the value on 7-segment 0 , 7-segment 1 and so on 83
- 84. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab2: Use MAX7221 to send a sequence Number to eight 7-segment 84
- 85. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_systemLab2: Use MAX7221 to send a sequence Number to eight 7-segment 85
- 86. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Lab2: Use MAX7221 to send a sequence Number to eight 7-segment Solution 86
- 87. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system SPI Driver HTTPS://GITHUB.COM/KEROLES/EMBEDDED_SYSTEM/TREE/MASTER/ATMEGA32 _DRIVERS/ATMEGA32_DRIVERS/SPI 87
- 93. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Think in depth In your opinion, What is the main issue on this Driver ? 93
- 94. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Think in depth The main issue in this Driver is If you configure the Driver to run as SPI Slave, then the “SPI_Send_And_recieve” API will hang the SW “Blocking Code” until the SPI master trigger a transaction 94
- 95. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Think in depth You can see we are using the C enum in the Driver, We can make all the SPI Configuration by using the macros instead of the enum In your opinion What makes a better constant in C, a macro or an enum? 95
- 96. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system Think in depth In terms of readability, enumerations make better constants than macros, because related values are grouped together. In addition, enum defines a new type, so the readers of your program would have easier time figuring out what can be passed to the corresponding parameter. A macro is a preprocessor thing, and the compiled code has no idea about the identifiers you create. They have been already replaced by the preprocessor before the code hits the compiler. An enum is a compile time entity, and the compiled code retains full information about the symbol, which is available in the debugger (and other tools). Prefer enums (when you can). 96
- 97. https://www.facebook.com/groups/embedded.system.KS/ Follow us Press here #LEARN_IN DEPTH #Be_professional_in embedded_system References https://www.newbiehack.com/MicrocontrollersABeginnersGuideIntroductionandInterfacinganLC D.aspx http://www.slideshare.net/MathivananNatarajan/asynchronous-serial-data-communication-and- standards https://www.slideshare.net/AnkitSingh13/uart-32550652 the avr microcontroller and embedded. System using assembly and c. Muhammad Ali Mazidi Embedded Systems lectures “Engr. Rashid Farid Chishti” https://www.corelis.com/education/SPI_Tutorial.htm http://ftm.futureelectronics.com/2014/09/nxp-macronics-nor-series-quad-spi-flash-a-simpler-faster- alternative-to-standard-spi-flash-when-adding-external-memory-to-32-bit-mcu-systems/ http://www.byteparadigm.com/products/spi-storm/spi-storm-advanced-information/ https://stackoverflow.com/questions/17125505/what-makes-a-better-constant-in-c-a-macro-or-an- enum 97