Part-1 : Mastering microcontroller with embedded driver development
- 1. Mastering Microcontroller with Embedded Driver Development FastBit Embedded Brain Academy Check all online courses at www.fastbitlab.com PART-1
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- 4. Section Takeaways ! This section has totally 7 lectures You will learn about behind the scene implementation about GPIO pin and GPIO port GPIO Input mode configurations like HIGH-Z , pull-up,pull-down state You will learn about different GPIO output Configurations like Open drain, pushpull , etc. You will learn about I/O power optimization
- 5. GPIO Pin and GPIO Port
- 8. GPIOs typically used for
- 9. Let’s begin with some of the must know concepts in GPIO. These concepts are generic and can be applied to any microcontroller you have !
- 10. GPIO Port A PA.0 PA.1 PA.15 Port ‘A’ having many pins Port ‘Soller Town’ having many boats
- 11. Each port have 8 i/o pins Each port have 32 i/o pins Each port have 16 i/o pins
- 12. GPIO Pin Behind the Scene
- 13. How does a GPIO pin is actually implemented inside the MCU?
- 14. Enable Line Output buffer Input buffer Pin YOUR MCU
- 15. Enable Line Output buffer Input buffer Pin MCU GND +VCC Pin T1 T2 gate gate source source drain PMOS NMOS
- 16. Enable Line Output buffer Input buffer Pin MCU Pin +VCC T1 T2 G S S D P N
- 17. Enable Line Output buffer Input buffer Pin MCU Pin +VCC T1 T2 +VCC G S S D P N
- 18. Enable Line Output buffer Input buffer Pin MCU Pin +VCC T1 T2 G S S D P N
- 19. GPIO INPUT MODE High Impedance(HI-Z) State
- 20. High impedance is also called as HI-Z state Let’s understand, what exactly is this High Impedance state, that people talk about when the pin is in input mode ??
- 22. GPIO INPUT MODE Pull-Up/Pull-Down State
- 24. GPIO OUTPUT MODE Open-drain State
- 27. GPIO OUTPUT MODE Open drain with Pull-Up
- 28. GND Ri +VCC Pin GND Re +VCC Pin Open drain with internal pull up Open drain with External pull up G S D P G S D P
- 29. Practical Usage -1 How to drive a LED from Open drain GPIO Pin ??
- 30. GND Pin +VCC GNDGND LED Pin R Driving LED’s Using External Pull-up +VCC R Using Internal Pull-up GND LED G S D N G S D N
- 31. Practical Usage -2 Driving I2C bus
- 32. Serial Clock line(SCL) +Vcc Serial Data Line(SDA) GND GND MCU Pin Pin SDA Rx SDA Tx SCL Rx SCL Tx SCL Pull-Up SDA Pull-Up I2C Bus S N G D S N G D
- 33. GPIO OUTPUT MODE Push-Pull State
- 34. GND +VCC PinT1 T2 G S D N S P Output Mode with Push-Pull Configuration
- 35. GND Ri +VCC Pin GND Re +VCC Pin Open drain with internal pull up Open drain with External pull up G S D P G S D P
- 36. How to drive a LED from Push-Pull GPIO Pin ??
- 38. GND +VCC Pin LED_GREEN R T1 T2 G S N S P D PD12 Discovery Board LED Connection
- 39. Optimizing IO Power Consumption Leakage Mechanism By Input Pin Floating
- 40. MCU Pin +VCC +VCC MCU Pin +VCC Fixed to High Fixed to Low GND GND GND T1 T2 T1 T2 G S N S P D S N S P D G
- 41. MCU Pin +VCC T1 T2 Voltage of input is not fixed May be 0.5Vcc or 0.3Vcc GND GND D S N S P G Input Logic Level
- 42. Valve opened partially Water Tickles out Valve Closed No water flows
- 44. Port Direction(Mode) register I/O PORT BUS Port Speed Register Port output type Register Some other configuration Register Port OutPut Data Register Port Input Data Register MCU I/0 Pins
- 45. In STM32F4xx series of microcontrollers, each GPIO port is governed by many configuration registers.
- 46. Exploring GPIO Port and Pins On the Discovery board
- 47. GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH GPIOI GPIOA GPIOB GPIOC GPIOD GPIOE Each port will have its Own set of configuration registers STM32F407VG
- 50. GPIO Port MODE Register
- 51. GPIOA_MODER GPIOB_MODER GPIOC_MODER GPIOD_MODER GPIOE_MODER GPIOF_MODER GPIOG_MODER GPIOH_MODER GPIOI_MODER 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg. 32 bit reg.
- 52. Before using any GPIO, you must decide its MODE. Whether you want to use it as an Input, Output or for any analog purposes
- 53. An MCU GPIO Pin INPUT OUTPUT ALT. FUN. ANALOG INTERRUPT When MCU pin is in INPUT mode it can be configured to issue an interrupt to the processor A GPIO Pin can be used for many purposes as shown here . That’s why it is called as “General” Purpose. Some pins of the MCU can not be used for all these purposes. So those are called as just pins but not GPIOs
- 55. Input mode : Summary When the I/O port is programmed as Input: the output buffer is disabled the Schmitt trigger input is activated the pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle A read access to the input data register provides the I/O State
- 56. Floating input
- 59. Output configuration ( Push pull)
- 60. Output configuration ( Push pull)
- 61. Output configuration ( Open Drain)
- 63. GPIO Port Output Type Register
- 64. When a GPIO pin is in the output mode, this register is used to select the output type of that pin
- 65. GPIO Port Speed Register
- 66. By using speed register you can configure “how quick the GPIO transitions from H to L and L to H” In other words you can control the slew rate of a pin
- 68. LOW Slew rate
- 69. MEDIUM Slew rate
- 70. HIGH Slew rate
- 73. Applicability of SPEED register configuration Pin Mode = OUTPUT Applicable
- 74. Applicability of SPEED register configuration Pin Mode = INPUT Don’t care So, Speed setting is only applicable when the pin is in output mode
- 76. GPIO Port Input Data Register
- 77. GPIO Port Output Data Register
- 78. GPIO Functional Summary By taking various modes and pull up /pull down resistors combinations below configurations can be obtained for a GPIO pin Input floating Input pull-up Input-pull-down Analog Output open-drain with pull-up or pull-down capability Output push-pull with pull-up or pull-down capability Alternate function push-pull with pull-up or pull-down capability Alternate function open-drain with pull-up or pull-down capability
- 79. Alternate Functionality configuration of a GPIO pin
- 80. An MCU GPIO Pin INPUT OUTPUT ALT. FUN. ANALOG INTERRUPT When a GPIO is in Alternate functionality mode it can be used for 16 different functionalities .
- 81. A GPIO Pin’s 16 possible alternate functionalities
- 82. Exercise : List out all the 16 possible alternation functionalities supported by GPIO port ‘A’ pin number 8 (GPIOA.8) MODE(Afx) Functionality AF0 MCO1 AF1 TIM1_CH1 AF2 Not Supported AF3 Not Supported AF4 I2C3_ SCL AF5 Not Supported AF6 Not Supported AF7 USART1_ CK
- 83. Exercise : List out all the 16 possible alternation functionalities supported by GPIO port ‘A’ pin number 8 (GPIOA.8) MODE(Afx) Functionality AF8 Not Supported AF9 Not Supported AF10 OTG_FS_ SOF AF11 Not Supported AF12 Not Supported AF13 Not Supported AF14 Not Supported AF15 EVENT OUT
- 84. Exercise : List out all the alternation functionalities supported by GPIO port ‘C’ pin number 6 (GPIOC.6)
- 85. Solution : List out all the alternation functionalities supported by GPIO port ‘C’ pin number 6 (GPIOC.6) MODE(Afx) Functionality AF0 Not Supported AF1 Not Supported AF2 TIM3_CH1 AF3 TIM8_CH1 AF4 Not Supported AF5 I2S2_MCK AF6 Not Supported AF7 Not Supported
- 86. Solution : List out all the alternation functionalities supported by GPIO port ‘C’ pin number 6 (GPIOC.6) MODE(Afx) Functionality AF8 USART6_TX AF9 Not Supported AF10 Not Supported AF11 Not Supported AF12 SDIO_D6 AF13 DCMI_D0 AF14 Not Supported AF15 EVENT OUT
- 88. Example Find out the alternate functionally mode(AFx) and AFR(Alternate Function Register) settings to make PA0 as UART4_TX PA1 as UART4_RX PA10 as TIM1_CH3
- 89. Solution: PA0 as UART4_TX AFx = AF8 ( This info you can only get from datasheet of the MCU not from RM in the case of ST’s MCUs)
- 90. Solution: PA0 as UART4_TX AFR settings GPIOA_AFRL
- 91. Solution: PA1 as UART4_RX AFx = AF8 GPIOA_AFRL
- 92. Solution: PA10 as TIM1_CH3 AFx = AF1 GPIOA_AFRH
- 95. Enabling /Disabling GPIO Port Peripheral Clock
- 96. RCC Peri. Clock Enable Registers RCC_AHB1ENR RCC_AHB2ENR RCC_AHB3ENR RCC_APB1ENR RCC_APB2ENR
- 100. SPIGPIO UARTI2C STM3F407x MCU gpio_driver.c , .h spi_driver.c , .h i2c_driver.c , .h uart_driver.c , .h Stm3f407xx.h Driver Layer Sample Applications (Device header)
- 101. SPIGPIO UARTI2C STM3F407x MCU gpio_driver.c , .h spi_driver.c , .h i2c_driver.c , .h uart_driver.c , .h Stm3f407xx.h Driver Layer Sample Applications (Device header) 1 2 3
- 102. What is Device Header file and what it contains ? This is a header file (‘C’ header file in our case) which contains Microcontroller specific details such as 1) The base addresses of various memories present in the microcontroller such as (Flash, SRAM1,SRAM2,ROM,etc) 2) The base addresses of various bus domains such as (AHBx domain, APBx domain) 3) Base addresses of various peripherals present in different bus domains of the microcontroller 4) Clock management macros ( i.e clock enable and clock disable macros) 5) IRQ definitions 6) Peripheral Register definition structures 7) Peripheral register bit definitions 8) Other useful microcontroller configuration macros
- 103. Stm3f407xx.h (Device header) Application Driver files Application and Driver source files can #include device specific header file to access MCU specific details
- 104. In the next lecture lets create MCU Device specific header file step by step
- 105. New project creation
- 106. Define base addresses of MCU embedded memories using ‘C’ macros
- 107. Defining base addresses of various bus domains (AHBx , APBx)
- 108. PERIPH_BASE APB1PERIPH_BASE APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE •Different peripherals are hanging on different busses . •AHB bus is used for those peripherals which need high speed data communication (ex. Camera interfaces, GPIOs) •APB bus is used for those peripherals for which low speed communication would suffice . Different bus domains of the stm32f4x MCU .
- 109. 0x0000_0000 0xFFFF_FFFFFull Memory map of the MCU 0x0000_0004 Offset between 2 memory addresses is 4 bytes 32 bits wide 32 bits wide 32 bits wide 0x40000000 (PERIPH_BASE)(APB1PERIPH_BASE) From here onwards peripheral register addresses start
- 110. 0x0000_0000 0xFFFF_FFFFFull Memory map of the MCU 0x0000_0004 Offset between 2 memory addresses is 4 bytes 32 bits wide 32 bits wide 32 bits wide 0x40000000 (PERIPH_BASE)(APB1PERIPH_BASE) From here onwards peripheral register addresses start Find out 0x4000_0000 is the address of which register of which peripheral ????
- 111. PERIPH_BASE (APB1PERIPH_BASE) APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE 0x40000000 Offset : 0x00010000 0x40010000 Offset : 0x00020000 0x40020000 Offset:0x10000000 0x50000000 Figure shows Peripheral base addresses of different bus domains In stm32f407xx MCU This simply means that registers of peripherals hanging on APB2 bus will appear on address 0x40010000 onwards in the memory map of the MCU.
- 112. Defining base addresses of AHB1 peripherals, APB1 and APB2 peripherals
- 113. AHB1 APB1 APB2 GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI I2C1 I2C2 I2C3 SPI2 SPI3 USART 2 USART 3 UART4 UART5 SPI1 USART 1 USART 6 EXTI SYSCF G
- 114. Addresses of the peripheral registers
- 115. PERIPH_BASE APB1PERIPH_BASE APB2PERIPH_BASE AHB1PERIPH_BASE AHB2PERIPH_BASE GPIOA 0x40000000 0x40020000 0x4002 0000 MODE Reg. OUTPUT TYPE Reg. SPEED Reg. PUPDR Reg. IDR Reg. ODR Reg. BSRR Reg. 0x00Offset: 0x04 0x08 0x0C 0x10 0x14 0x18 0x40020000 0x40020004 0x40020008 0x4002000C 0x40020010 0x40020014 0x40020018 Determining addresses of various registers of a peripheral
- 116. Exercise: Find out the addresses of below registers of SPI1 peripheral . Register Name Address control register 1 ?? control register 2 ?? status register ?? data register ?? CRC polynomial register ?? RX CRC register ?? TX CRC register ?? configuration register ?? prescaler register ??
- 117. Structuring Peripheral register details
- 118. Example : ‘C’ Structure for registers of GPIO peripheral Variable(Place holder) to hold values for GPIOx_MODE register and so on
- 119. Base address of GPIOA Address of MODER variable(&MODER) will be (0x40020000+0x00) Address of OTYPER variable(&OTYPER ) will be (0x40020000+0x04) and so on
- 122. Peripheral clock enable and disable macros
- 123. Macros for IRQ(Interrupt Request) Numbers of the MCU
- 124. Creating GPIO Driver .c and .h files
- 125. GPIO Handle and Configuration structures
- 126. GPIOx Peripheral GPIO mode GPIO speed GPIO Pullup-pulldown GPIO outputtype GPIO Pin number GPIO Port Name Configurable items For user application GPIO Alt.function mode
- 127. GPIO Driver APIs requirements
- 128. GPIO Driver APIs GPIO initialization Enable/Disable GPIO port clock Read From a GPIO Pin Write to GPIO Pin Configure alternate functionality Interrupt Handling Driver API Requirements
- 129. GPIO Pin Interrupt Configuration 1. Pin must be in input configuration 2. Configure the edge trigger (RT,FT,RFT) 3. Enable interrupt delivery from peripheral to the processor (on peripheral side) 4. Identify the IRQ number on which the processor accepts the interrupt from that pin 5. Configure the IRQ priority for the identified IRQ number (Processor side) 6. Enable interrupt reception on that IRQ number (Processor side) 7. Implement IRQ handler
- 130. STM32f4x GPIO Pins interrupt delivery to the Processor N V I C Processor core EXTI EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 EXTI5_9 EXTI10_15 5 6 GPIOx_PIN0 GPIOx_PIN1 GPIOx_PIN2 GPIOx_PIN3 GPIOx_PIN4 GPIOx_PIN5_9 GPIOx_PIN10_15 6 7 8 9 10 23 40 Processor side MCU Peripheral side EXTI block does Edge detection(FT,RT) , Enable/Disable of interrupt delivery to the processor Enable/Disable of IRQs are configured in NVIC registers GPIO port is decided by SYSCFG_EXTICR register configuration
- 134. IRQ0IRQ1IRQ2IRQ9IRQ15 IRQ16IRQ31 Interrupt Set-enable Registers NVIC_ISER0 0 has no effect 1 enables the interrupt
- 135. IRQ32IRQ33IRQ34 IRQ41IRQ47 IRQ48IRQ63 Interrupt Set-enable Registers NVIC_ISER1 0 has no effect 1 enables the interrupt
- 136. IRQ64IRQ65IRQ66 IRQ80IRQ95 Interrupt Set-enable Registers NVIC_ISER2 0 has no effect 1 enables the interrupt
- 137. IRQ0IRQ1IRQ2IRQ9IRQ15 IRQ16IRQ31 Interrupt Clear-enable Registers NVIC_ICER0 0 has no effect 1 disable interrupt
- 139. Exercise Write a program to toggle the on board LED with some delay . Case 1 : Use push pull configuration for the output pin Case 2 : Use open drain configuration for the output pin
- 140. Discovery Board LEDs
- 142. USBLogicanalyzer CH0CH1GND To PC Probing LED Toggling using USB Logic Analyzer
- 143. Exercise Write a program to toggle the on board LED whenever the on board button is pressed
- 144. Exercise Write a program to connect external button to the pin number PB12 and external LED to PA14 Toggle the LED whenever the external button is pressed
- 146. Exercise Toggle a GPIO pin with no delay between GPIO high and GPIO low and measure the frequency of toggling using logic analyzer
- 147. Exercise Connect an external button to PD5 pin and toggle the led whenever interrupt is triggered by the button press. Interrupt should be triggered during falling edge of button press.
- 148. In the next lecture lets understand input mode of a pin
- 149. Introduction to SPI
- 151. SCLK MOSI MISO ss SCLK MOSI MISO gpio1 Master Slave ( Sensor, EEPROM, SDCARD, Display, Bluetooth,etc ) The SPI bus allows the communication between one master device and one or more slave devices. SPI Bus Master Out Slave In Master In Slave Out Slave Control Serial Clock
- 152. SCLK MOSI MISO ss SCLK MOSI MISO gpio1 Master Slave ( Sensor, EEPROM, SDCARD, Display, Bluetooth,etc ) Master Out Slave In Master In Slave Out Slave Control Serial Clock 1. Four I/O pins are dedicated to SPI communication with external devices. 2. MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data in slave mode and receive data in master mode 3. MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data in master mode and receive data in slave mode. 4. SCK: Serial Clock output pin for SPI master and input pin for SPI slaves. 5. NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to select an individual slave device for communication
- 154. Protocol Type Max distance(ft.) Max Speed (bps) Typical usage USB 3.0 dual simplex serial 9 (typical) (up to 49 with 5 hubs) 5 G Mass storage, video USB 2.0 half duplex serial 16 (98 ft. with 5 hubs) 1.5M, 12M, 480M Keyboard, mouse, drive, speakers, printer, camera Ethernet serial 1600 10G network communications I2C synchronous serial 18 3.4 M in High-speed mode. Microcontroller communications RS-232 asynchronous serial 50–100 20k Modem, mouse, instrumentation RS-485 asynchronous serial 4000 10M Data acquisition and control systemsSPI SPI synchronous serial 10 fPCLK/2
- 156. You can use CAN, ETHERNET , RS485, RS232 or combination of them , when you have to cover larger distances and want to achieve better quality of service.
- 159. MINIMAL SPI BUS The SPI bus allows the communication between one master device and one or more slave devices. In some applications SPI bus may consists of just two wires - one for the clock signal and the other for synchronous data transfer. Other signals can be added depending on the data exchange between SPI nodes and their slave select signal management. SCLK MOSI MISO ss SCLK MOSI MISO Master SlaveMaster Out Slave In Serial Clock gpio
- 160. SPI Hardware :Behind the scenes
- 161. MOSI MISO SCLK A 6 A 5 A 4 A 7 A 3 A 2 A 1 A 0 Master Shift Register B 6 B 5 B 4 B 7 B 3 B 2 B 1 B 0 Slave Shift Register SCLK SPI Hardware :Behind the scenes SPI clock generator
- 162. MOSI MISO Slave SCLK 1 A 7 A 6 A 5 B 0 A 4 A 3 A 2 A 1 Master Shift Register B 7 B 6 B 5 A 0 B 4 B 3 B 2 B 1 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 163. MOSI MISO SCLK 1 2 B 0 A 7 A 6 B 1 A 5 A 4 A 3 A 2 Master Shift Register A 0 B 7 B 6 A 1 B 5 B 4 B 3 B 2 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 164. MOSI MISO Slave SCLK 1 2 3 B 1 B 0 A 7 B 2 A 6 A 5 A 4 A 3 Master Shift Register A 1 A 0 B 7 A 2 B 6 B 5 B 4 B 3 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 165. MOSI MISO Slave SCLK 1 2 3 4 B 2 B 1 B 0 B 3 A 7 A 6 A 5 A 4 Master Shift Register A 2 A 1 A 0 A 3 B 7 B 6 B 5 B 4 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 166. MOSI MISO SCLK 1 2 3 4 5 B 3 B 2 B 1 B 4 B 0 A 7 A 6 A 5 Master Shift Register A 3 A 2 A 1 A 4 A 0 B 7 B 6 B 5 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 167. MOSI MISO Slave SCLK 1 2 3 4 5 6 B 4 B 3 B 2 B 5 B 1 B 0 A 7 A 6 Master Shift Register A 4 A 3 A 2 A 5 A 1 A 0 B 7 B 6 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 168. MOSI MISO SCLK 1 2 3 4 5 6 7 B 5 B 4 B 3 B 6 B 2 B 1 B 0 A 7 Master Shift Register A 5 A 4 A 3 A 6 A 2 A 1 A 0 B 7 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 169. MOSI MISO SCLK 1 2 3 4 5 6 7 8 B 6 B 5 B 4 B 7 B 3 B 2 B 1 B 0 Master Shift Register A 6 A 5 A 4 A 7 A 3 A 2 A 1 A 0 Slave Shift Register SPI Hardware :Behind the scenes SCLKSPI clock generator
- 170. CUSTOMIZING SPI BUS : BUS CONFIGURATIONS The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements.
- 171. Up to 16-bit shift register Up to 16-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit In this configuration, the shift registers of the master and slave are linked using two unidirectional lines between the MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the SCK clock edges provided by the master. The master transmits the data to be sent to the slave via the MOSI line and receives data from the slave via the MISO line. By default, the SPI is configured for full- duplex communication FULL-DUPLEX COMMUNICATION
- 172. Remember that in SPI communication ,slave will not initiate data transfer unless master produces the clock.
- 173. 8-bit shift register 8-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit R HALF -DUPLEX COMMUNICATION In this configuration, one single cross connection line is used to link the shift registers of the master and slave together. During this communication, the data is synchronously shifted between the shift registers on the SCK clock edge in the transfer direction selected reciprocally by both master and slave
- 174. 8-bit shift register 8-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit SIMPLEX COMMUNICATION Simplex single master, single slave application (master in transmit-only/slave in receive-only mode) Transmit-only , Receive Only mode : The configuration settings are the same as for full- duplex. The application has to ignore the information captured on the unused input pin. This pin can be used as a standard GPIO
- 175. STM32 SPI FUNCTIONAL BLOCK DIAGRAM
- 177. SLAVE SELECT (NSS) PIN MANAGEMENT When a device is slave mode: In slave mode, the NSS works as a standard “chip select” input and lets the slave communicate with the master. When a device is master: In master mode, NSS can be used either as output or input. As an input it can prevent multi-master bus collision, and as an output it can drive a slave select signal of a single slave.
- 178. 8-bit shift register 8-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit Scenario of single master and single slave
- 179. Hardware slave management Software slave management 2 Types of slave managements
- 180. 8-bit shift register 8-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit Scenario of single master and single slave Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register: Software NSS management (SSM = 1): in this configuration, slave select information is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is free for other application uses.
- 181. 8-bit shift register 8-bit shift register SPI Clock generator Master Slave MISO MISO MOSI MOSI SCK SCK NSS NSS MSBit LSBbit MSBit LSBbit Scenario of single master and single slave Hardware or software slave select management can be set using the SSM bit in the SPIx_CR1 register: Hardware NSS management (SSM = 0): Nss pin must be pulled low to active salve to communicate with master Hardware NSS management (SSM = 0): Nss pin must be in output mode. The NSS pin is managed by the hardware
- 182. In this application you cannot use software slave management . You have to use hardware slave management
- 184. SPI Communication Format SCLK PHASE(CPHA) SCLK POLARITY(CPOL) Data frame format(DFF) •During SPI communication, receive and transmit operations are performed simultaneously. •The serial clock (SCK) synchronizes the shifting and sampling of the information on the data lines •The communication format depends on the clock phase, the clock polarity and the data frame format. To be able to communicate together, the master and slaves devices must follow the same communication format.
- 185. CPOL(CLOCK POLARITY) The CPOL (clock polarity) bit controls the idle state value of the clock when no data is being transferred If CPOL is reset, the SCLK pin has a low-level idle state. If CPOL is set, the SCLK pin has a high-level idle state.
- 186. CPOL =1 CPOL =0
- 187. CPHA(CLOCK PHASE) CPHA controls at which clock edge of the SCLK( 1st or 2nd ) the data should be sampled by the slave. The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data capture clock edge.
- 188. Data toggling means, data transition to the next bit. Data sampling means, sampling the data line to capture the data. 1 0 1 1 10 Data line Data line Clock
- 189. CPHA=1 Data will appear on the lines during first edge of the SCLK1
- 190. CPHA=1 Slave captures the data here ( 2nd edge of the SCLK)2
- 191. CPHA=1 Data will appear on the lines during first edge of the SCLK 1 H L
- 192. CPHA=0 Data will appear on the lines during 2nd edge of the lock1
- 193. CPHA=0 Slave captures the data here ( 1st edge of the SCLK)2
- 194. Different SPI Modes
- 195. If CPHASE=1 Data will be sampled on the trailing edge of the clock. If CPHASE=0 Data will be sampled on the leading edge of the clock.
- 196. SPI peripherals of your MCU AHB1 APB1 APB2 GPIOA GPIOB GPIOC GPIOD GPIOE …. GPIOI I2C1 I2C2 I2C3 SPI2 SPI3 USART 2 USART 3 UART4 UART5 SPI1 USART 1 USART 6 EXTI SYSCF G
- 197. SPI serial clock (SCLK)
- 198. What is the maximum SCLK speed of SPIx peripheral which can be achieved on a given microcontorller ? First you have to know the speed of the APBx bus on which the SPI peripheral is connected
- 199. / APB 1 bus ( 42 Mhz Max) SPI2/SPI3 HSI HSE PLL 16MHz / Min Prescalar = 2 8MHz SCLK fpclk = 16MHz APB1 bus prescalar
- 200. / APB 2 bus ( 84 Mhz Max) SPI1 HSI HSE PLL 16MHz / Min Prescalar = 2 8MHz SCLK fpclk = 16MHz APB2 bus prescalar
- 201. So, if we use the internal RC oscillator of 16Mhz as our system clock then SPI1/SPI2/SPI3 peripherals can able to produce the serial clock of maximum 8MHz.
- 202. Remember that in SPI communication ,slave will not initiate data transfer unless master produces the clock.
- 204. Driver API requirements and user configurable items
- 205. SPIGPIO UARTI2C STM3F407x MCU gpio_driver.c , .h spi_driver.c , .h i2c_driver.c , .h uart_driver.c , .h Stm3f407xx.h Driver Layer Sample Applications (Device header)
- 206. SPI Driver API s SPI Initialization / peripheral clock control SPI TX SPI RX SPI Interrupt config. & handling Other SPI management APIs
- 207. SPIx Peripheral SPI_DFF SPI_CPHA SPI_SSM SPI_CPOL SPI_BusConfig SPI_DeviceMode Configurable items For user application SPI_Speed
- 208. SPI handle structure and configuration structure
- 209. SPI Configuration Structure SPI Handle Structure
- 210. Exercise : 1. Complete SPI register definition structure and other macros ( peripheral base addresses, Device definition , clock en , clock di , etc) in MCU specific header file 2. Complete SPI Configuration structure and SPI handle structure in SPI header file
- 212. Send data Len=0 ? Wait until the Tx buffer is empty DFF ? Load DR with 1 byte of data And increment the buffer address Len-- Load DR with 1 byte of data And increment the buffer adress Len-- Exit from the function Start End No Yes 16 bit 8Bit 1 0
- 213. Receive data Len=0 ? Wait until the Rx Buffer is non empty DFF ? Read DR for 1 byte of data And increment the rx buffer address Len-- Read DR for 2 bytes of data And increment the rx buffer address Len-- Exit from the function Start End No Yes 16 bit 8Bit 1 0
- 214. Exercise : 1. Test the SPI_SendData API to send the string “Hello world” and use the below configurations 1. SPI-2 Master mode 2. SCLK = max possible 3. DFF = 0 and DFF = 1
- 215. Exercise : SPI Master(STM) and SPI Slave(Arduino) communication . When the button on the master is pressed , master should send string of data to the Arduino slave connected. The data received by the Arduino will be displayed on the Arduino serial port. 1 .Use SPI Full duplex mode 2. ST board will be in SPI master mode and Arduino will be configured for SPI slave mode 3. Use DFF = 0 4. Use Hardware slave management (SSM = 0) 5. SCLK speed = 2MHz , fclk = 16MHz In this exercise master is not going to receive anything for the slave. So you may not configure the MISO pin Note. Slave does not know how many bytes of data master is going to send. So master first sends the number bytes info which slave is going to receive next.
- 216. Things you need ST board Arduino boardSPI USB PC ( Arduino Serial Monitor ) 1 .Arduino board 2. ST board 3. Some jumper wires 4. Bread board
- 217. STEP-1 Connect Arduino and ST board SPI pins as shown
- 218. STEP-2 Power your Arduino board and download SPI Slave sketch to Arduino Sketch name : 001SPISlaveRxString.ino
- 219. Find out the GPIO pins over which SPI2 can communicate
- 220. Exercise : SPI Master(STM) and SPI Slave(Arduino) command & response based communication . When the button on the master is pressed, master sends a command to the slave and slave responds as per the command implementation . 1 .Use SPI Full duplex mode 2. ST board will be in SPI master mode and Arduino will be configured for SPI slave mode 3. Use DFF = 0 4. Use Hardware slave management (SSM = 0) 5. SCLK speed = 2MHz , fclk = 16MHz
- 221. Connect Arduino and ST board SPI pins as shown STEP-1
- 222. STEP-2 Power your Arduino board and download SPI Slave sketch to Arduino Sketch name : 002SPISlaveCmdHandling.ino
- 223. Master Slave Master sends a command ACK or NACK BYTESlave response Take action according to command IF NACK Display error message Slave response for data read command Master & Slave communication 1 or more Command ArgumentsIF ACK NACK 0xA5 ACK 0xF5
- 224. Command formats < command_code(1) > <arg1 > <arg2> 1)CMD_LED_CTRL <pin no(1)> <value(1)> 2)CMD_SENOSR_READ <analog pin number(1) > 3) CMD_LED_READ <pin no(1) > 4) CMD_PRINT <len(2)> <message(len) > 5) CMD_ID_READ This command is used to turn on/off led connected to specified arduino pin number ON/OFF
- 225. CMD_LED_CTRL <pin no> <value> <pin no > digital pin number of the arduino board ( 0 to 9) ( 1 byte) <value> 1 = ON , 0 = OFF (1 byte) Slave Action : control the digital pin ON or OFF Slave returns : Nothing
- 226. Remove the connection made here Download the code Then, connect it back
- 227. CMD_SENOSR_READ <analog pin number > <analog pin number > Analog pin number of the Arduino board ( A0 to A5) (1 byte) Slave Action : Slave should read the analog value of the supplied pin Slave returns : 1 byte of analog read value
- 228. CMD_LED_READ <pin no > <pin no > digital pin number of the arduino board ( 0 to 9) Slave Action : Read the status of the supplied pin number Slave returns : 1 byte of led status . 1 = ON , 0 = OFF
- 229. CMD_PRINT <len> <message > <len> 1 byte of length information of the message to follow <message> message of ‘len’ bytes Slave Action : Receive the message and display via serial port Slave returns : Nothing
- 230. CMD_ID_READ No arguments for this command Slave returns : 10 bytes of board id string
- 231. Application flow chart START Enter main() All inits Wait till button is pressed Execute CMD_LED_CTRL Wait till button is pressed Execute CMD_SENSOR_READ Wait till button is pressed Execute CMD_LED_READ
- 234. APB1/APB2 Firmware Write 0xAB Shift Register Rx buffer TX buffer Read Write Data Register
- 235. APB1/APB2 Firmware Write 0xAB Shift Register Rx buffer TX buffer Read Write Data Register
- 236. APB1/APB2 Firmware Read 0xAB Shift Register Rx buffer TX buffer Read Write Data Register
- 237. SPI interrupts During SPI communication , interrupts can be generated by the following events: • Transmit Tx buffer ready to be loaded • Data received in Rx buffer • Master mode fault ( in single master case you must avoid this error happening ) • Overrun error Interrupts can be enabled and disabled separately.
- 238. SPI interrupts
- 239. NVIC Processor Core SPI_1 SPI_2 SPI_3 ARM Cortex M4 MCU SPI Interrupting the Processor
- 240. Exercise-1 Complete SPI IRQ number definition macros in MCU specific header file
- 241. Exercise-2 Complete the SPI IRQ Configuration APIs Implementation (reuse code from GPIO driver)
- 242. SPI send data API (Interrupt mode)
- 243. API to send data with interrupt mode
- 244. API to send data with interrupt mode So first we have to create some place holder variables to save application’s Tx address, len and SPI state.
- 246. Possible SPI Application States #define SPI_READY 0 #define SPI_BUSY_IN_RX 1 #define SPI_BUSY_IN_TX 2
- 247. SPI receive data API (Interrupt mode)
- 248. SPI receive data with interrupt
- 249. SPI ISR Handling Implementation
- 250. Enter ISR Understand which event caused interrupt to trigger(check SR) Interrupt is due to setting of RXNE flag Interrupt is due to setting of TXE flag Interrupt is due Setting of ERROR flag Handle RXNE event Handle TXE flag Handle Error Handling SPI interrupt in the Code
- 251. Handling TXE interrupt Handle TXE interrupt Write one byte to SPI Data register(DR) Write 2 byte to SPI Data register(DR) Len-- Len -= 2 8 bit or 16 bit mode? Len = 0 ? Close the SPI TX Wait till another TXE interrupt 8bit 16bit Yes No Transmission over Transmission Not over
- 252. Configuring NSS
- 254. In STM32F4xx based microcontroller, the NSS pin can be handled by 2 ways Software Slave Management Hardware Slave Management
- 255. Software Slave Management SCLK MOSI MISO Nss Slave NSS Pin state is handled by ‘SSI’ bit in the CR1 register If SSI bit = 1 , then NSS goes HIGH +VCC SSI=1
- 256. Software Slave Management SCLK MOSI MISO Nss Slave NSS state is handled by ‘SSI’ bit in the CR1 register If SSI bit = 1 , then NSS goes HIGH If SSI bit = 0, then NSS goes LOW SSI=0
- 257. Software Slave Management SCLK MOSI MISO Nss SlaveSSI bit is the handle for the software to control the NSS pin ! NSS state is handled by ‘SSI’ bit in the CR1 register If SSI bit = 1 , then NSS goes HIGH If SSI bit = 0, then NSS goes LOW
- 258. So, What is the advantage of using Software Slave Management(SSM) ?
- 259. SCLK MOSI MISO Nss SCLK MOSI MISO gpio1 Master Sla ve Master need not use its another pin to drive the NSS pin low, that saves one pin for master. NSS pin is handled by SSI bit of Control register by software Saves PIN
- 260. What is Hardware slave Management?
- 262. Implementing Master rx API If master wants read something form the slave, it has to produce clock , and to produce clock Master has to place some data in to the tx buffer by writing some dummy bytes.
- 263. Implementing slave tx api Slave can not do Tx, until master produces clock Whenever you are in SPI slave mode and want to send some data, then slave must be ready with the data before master produces the clock.
- 264. Master Send Write CMD Master gets ACK bytes Master Sends Data Stream Verify ACK Pass Fail Blink RED LED Master Slave Verify Data Stream PassBlink BlueLED FailBlink RED LED Master Sending Write CMD and Data Stream to Slave
- 265. Send Read CMD Master gets ACK bytes from slave Master gets data stream from slave Verify ACK Pass Fail Blink RED LED Master Slave Verify Data Stream Pass Blink BlueLED Fail Blink RED LED Master Sending Read CMD and Receiving Data Stream From Slave
- 266. Master Write CMD Execution Master sends out the Write CMD Slave ACK back for the command If ACK is valid, then Master sends out the Data stream of known length Master Read CMD Execution Master sends out the Read CMD Slave ACK back for the command If ACK is valid , then Master gets the data stream from the slave of known length.
- 267. We selected spi2 device, The clock will run at 500KHz Data format is 8bit MSbfirst Spi mode is 0, because CPOL and CPHASE are 0 The peripheral acts as master device.
- 268. We selected SPI2 device. SPI serial line clock will run at 500KHz Data format is 8bit msb first SPI mode is 1, because CPO=0 and CPHASE=1 The peripheral acts as master device SPI Master Initialization SPI peripheral clock is 16Mhz, because we are running MCU at 16Mhz Internal RC Oscillator
- 269. Common Debugging Steps Master mode bit must be enabled in the configuration register if you are making peripheral to work in MASTER mode. SPI peripheral enable bit must be enabled SPI peripheral clock must be enabled
- 270. Common Problems in SPI and Debugging Tips
- 271. Master Can not able to produce clock and data Case 1
- 272. Case 1: Master cannot able to produce clock and data Reason-1: Non-Proper Configuration of I/O lines for Alternate functionality Debug Tip: Recheck the GPIO Configuration registers to see what values they have
- 273. Reason-2: Configuration Overriding Debug Tip: Dump out all the required register contents just before you begin the transmission Case 1: Master cannot able to produce clock and data
- 274. Master is sending data, but slave is not receiving data ! Case 2
- 275. Case 2: Master is sending data but slave is not receiving data ! Reason-1: Not pulling down the slave select pin to ground before sending data to the slave Debug Tip: Probe through the logic analyzer to confirm slave select line is really low during data communication
- 276. Reason-2 : Non-Proper Configuration of I/O lines for Alternate functionality Debug Tip: Probe the alternate function register Case 2: Master is sending data but slave is not receiving data !
- 277. Reason-3 : Non enabling the peripheral IRQ number in the NVIC Debug Tip: Probe the NVIC Interrupt Mask register to see whether the bit position corresponding to the IRQ number is set or not Case 2: Master is sending data but slave is not receiving data !
- 278. SPI interrupts are not getting triggered Case 3
- 279. Case 3: SPI interrupts are not getting triggered Reason-1 : Not enabling the TXE or RXNE interrupt in the SPI configuration register Debug Tip: Check the SPI configuration register to see TXEIE and RXNEIE bits are really set to enable the interrupt !
- 280. Reason-2: Non enabling the peripheral IRQ number in the NVIC Debug Tip: Probe the NVIC Interrupt Mask Register to see whether the bit position corresponding to the IRQ number is set or not Case 3: SPI interrupts are not getting triggered
- 281. Master is producing right data but slave is receiving the different data Case 4
- 282. Case 4: Master is producing right data but slave is receiving the different data Reason-1 : Using Long Wires in high frequency communication Debug Tip: use shorter wires or reduce the SPI serial frequency to 500KHz to check things work well
- 284. Cross Check These Settings Master mode bit must be enabled in the configuration register if you are configuring the peripheral as master SPI peripheral enable bit must be enabled . SPI peripheral clock must be enabled. By default clocks to almost all peripheral in the microcontroller will be disabled to save power.
- 285. Clock Sources in the MCU • High Speed Internal (HSI) oscillator • High Speed External (HSE) oscillator • Phase Locked Loop (PLL) • Low Speed Internal (LSI) clock • Low Speed External (LSE) clock
- 286. / VCO X / / / / / HSI HSE 16MHz 8 – 26 MHz PLLM PLLN PLLP PLLQ USB OTG,SDIO,etc SysClk AHB AHB APB1 APB2 PLL Clock Sources in the MCU
- 287. The HSI RC oscillator which is inside the MCU has the advantage of providing a clock source at low cost . Because there is no external components required to use this clock. It also has a faster start-up time than the external crystal oscillator however, the frequency is less accurate than an external crystal oscillator.
- 290. SPI2 SPI2 SCLK(PB13) MOSI(PB15) GND GND STM32F4 discovery STM32F4 discovery USER button Connection Diagram Master Slave SCLK(PB13) MISO(PB14) MISO(PB14) MOSI(PB15) NSS
- 291. How to enable the High Speed External Crystal Oscillator and use it as System Clock ?
- 292. Let’s measure the frequency of different clock sources like HSI,HSE,PLL by using USB logic Analyzer !
- 293. Connection between USB Logic Analyzer and Discovery board
- 295. SPI2 SPI2 SCLK(PB13) MOSI(PB15) GND GNDSTM32F4 discovery STM32F4 discovery USER button Master Slave SCLK(PB13) MISO(PB14) MISO(PB14) MOSI(PB15) USB Logic analyzer CH0CH1CH2GND To PC