cs1104 11
cs1104 11
Edge-Triggered Flip-flops
Asynchronous Inputs
2
Introduction
A sequential circuit consists of a feedback path,
and employs some memory elements.
Combinational outputs Memory outputs
Combinational logic
Memory elements
External inputs
Comparison
Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific time
Bistable logic devices: latches and flip-flops. Latches and flip-flops differ in the method used for
changing their state.
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Comparison
In synchronous circuits, memory elements are clocked FFs In synchronous circuits, the change in input signals can affect memory elements upon activation of clock signal. The maximum operating speed of the clock depends on time delays involved Easier to design.
In asynchronous circuits, memory elements are either unclocked FFs or time delay elements In asynchronous circuits, change input signals can affect memory elements at any instance of time Because of the absence of the clock, asynchronous circuits can operate faster than synchronous circuits. More difficult to design.
Memory Elements
Memory element: a device which can remember
value indefinitely, or change value on command from its inputs.
command Memory element Q stored value
Characteristic table:
Command (at time t) Set Reset Memorise / No Change Q(t) X X 0 1 Q(t+1)
Memory Elements
Memory element with clock. Flip-flops are memory
elements that change state on clock signals.
command
Memory element
Q stored value
clock
Positive edges
Negative edges
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Memory Elements
Two types of triggering/activation:
pulse-triggered
edge-triggered
Pulse-triggered
latches ON = 1, OFF = 0
Edge-triggered
flip-flops positive edge-triggered (ON = from 0 to 1; OFF = other
S-R Latch
Complementary outputs: Q and Q'. When Q is HIGH, the latch is in SET state. When Q is LOW, the latch is in RESET state. For active-HIGH input S-R latch (also known as NOR
gate latch), R=HIGH (and S=LOW) a RESET state S=HIGH (and R=LOW) a SET state both inputs LOW a no change both inputs HIGH a Q and Q' both LOW (invalid)!
S-R Latch
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S-R Latch
For active-LOW input S'-R' latch (also known as NAND
gate latch), R'=LOW (and S'=HIGH) a RESET state S'=LOW (and R'=HIGH) a SET state both inputs HIGH a no change both inputs LOW a Q and Q' both HIGH (invalid)!
S-R Latch
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S-R Latch
Characteristics table for active-high input S-R latch:
S 0 1 0 1 R 0 0 1 1 Q NC 1 0 0 Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition.
S R Q Q'
S-R Latch
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S-R Latch
Active-HIGH input S-R latch
10 100 R Q 11000 Q' 0 0 1 1 0
S 1 0 0 0 1 R 0 0 1 0 1 Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!
10 001 S
S'
Q Q'
S-R Latch
R'
S' R' 1 0 1 1 0 1 1 1 0 0
S EN
Q'
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Under what condition does the invalid state occur? Characteristic table:
EN=1
Q(t) 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 indeterminate 1 0 1 indeterminate
S R 0 0 1 1 0 1 0 1
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Gated D Latch
Make R input equal to S' gated D latch. D latch eliminates the undesirable condition of
invalid state in the S-R latch.
D EN Q'
D EN
Q
Q'
Gated D Latch
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Gated D Latch
When EN is HIGH,
D=HIGH latch is SET
Characteristic table:
EN 1 1 0 D 0 1 X Q(t+1) 0 1 Q(t) Reset Set No change
Gated D Latch
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Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices Output changes state at a specified point on a
triggering input called the clock.
Edge-Triggered Flip-flops
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Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops. Note the >
symbol at the clock input.
S C R Q' Q D C Q' Q J C K Q' Q
Q'
Q'
Q'
S-R Flip-flop
S-R flip-flop: on the triggering edge of the clock pulse,
S=HIGH (and R=LOW) a SET state R=HIGH (and S=LOW) a RESET state both inputs LOW a no change both inputs HIGH a invalid
S-R Flip-flop
It comprises 3 parts:
a basic NAND latch
a pulse-steering circuit
a pulse transition detector (or edge detector) circuit
SR Flip-flop
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S-R Flip-flop
The pulse transition detector.
S CLK Pulse transition detector R Q
Q'
CLK'
CLK CLK* CLK CLK' CLK* CLK
CLK'
CLK* CLK CLK' CLK*
D Flip-flop
D flip-flop: single input D (data)
D=HIGH a SET state
Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter.
D CLK S C R Q' Q
D 1 0 CLK Q(t+1) 1 0 Comments Set Reset
D Flip-flop
Application: Parallel data transfer.
To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.
D CLK X Q' D CLK Q' D Transfer CLK Q' * After occurrence of negative-going transition D Flip-flop 25 Q Q3 = Z* Q Q2 = Y* Q Q1 = X*
Y Z
J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulsesteering NAND gates.
J-K Flip-Ffop
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J-K Flip-flop
J-K flip-flop.
J CLK K Pulse transition detector Q
Q'
Characteristic table.
J 0 0 1 1 K 0 1 0 1 CLK Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle
Q 0 0 0 0 1 1 1 1
J K 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Q(t+1) 0 0 1 1 1 0 1 0
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T Flip-flop
T flip-flop: single-input version of the J-K flip flop,
formed by tying both inputs together.
T CLK Pulse transition detector Q
T CLK
J C K
Q Q'
Q'
Characteristic table.
T 0 1 CLK Q(t+1) Q(t) Q(t)' Comments No change Toggle
Q T 0 0 1 1 0 1 0 1 Q(t+1) 0 1 1 0
T Flip-flop
Application: Frequency division.
High J CLK C K CLK Q CLK QA QB Q CLK High J C K QA High J C K QB
Asynchronous Inputs
S-R, D and J-K inputs are synchronous inputs, as
data on these inputs are transferred to the flip-flops output only on the triggered edge of the clock pulse.
When PRE=HIGH, Q is immediately set to HIGH. When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop in normal operation mode when both PRE
and CLR are LOW.
Asynchronous Inputs
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Asynchronous Inputs
A J-K flip-flop with active-LOW preset and clear inputs.
PRE J PRE Q Pulse transition detector Q'
J C K
Q
CLK
Q'
K CLR
J = K = HIGH
Toggle
Clear 31
End of segment