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Basic VHDL Course: BY Shin Igneel

This document provides an overview of a basic VHDL course, including its goals, introduction to VHDL concepts, and features of the language. The course aims to provide comprehension of basic VHDL constructs, familiarity with VHDL design descriptions, and understanding of the VHDL timing model. VHDL is introduced as a hardware description language used for design specification, capture, simulation, documentation and as an alternative to schematics or proprietary languages. Key features highlighted include support for concurrent statements, libraries, sequential statements, hierarchy, generics, subprograms, type declarations, and timing control.

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Shin Igneel
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47 views19 pages

Basic VHDL Course: BY Shin Igneel

This document provides an overview of a basic VHDL course, including its goals, introduction to VHDL concepts, and features of the language. The course aims to provide comprehension of basic VHDL constructs, familiarity with VHDL design descriptions, and understanding of the VHDL timing model. VHDL is introduced as a hardware description language used for design specification, capture, simulation, documentation and as an alternative to schematics or proprietary languages. Key features highlighted include support for concurrent statements, libraries, sequential statements, hierarchy, generics, subprograms, type declarations, and timing control.

Uploaded by

Shin Igneel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Basic VHDL Course

BY Shin Igneel

Outline
Introduction Concepts and History of VHDL VHDL Models of Hardware VHDL Basics Summary

Course Goals
Comprehension of VHDL Basic Constructs

Familiarity with VHDL design descriptions

Understanding of the VHDL Timing Model

Introduction
Digital systems design process
Design Idea

Behavioral Design
Flow Graph, Pseudo Code, ...

Data Path Design


Bus & Register Structure

Logic Design
Gate Wirelist, Netlist

Physical Design
Transistor List, Layout, ...

Manufacturing Chip or Board

Sample Design Process


* Problem Design a single bit half adder with carry and enable * Specifications - Passes results only on enable high - Passes zero on enable low - Result gets x plus y - Carry gets any carry of x plus y
x y enable
carry result

Half Adder

Behavioral Design
* Starting with an algorithm, a high level description of the adder is created.

IF enable = 1 THEN result = x XOR y carry = x AND y ELSE carry = 0 result = 0

X y enable

carry Half Adder result

* The model can now be simulated at this high level description to verify correct understanding of the problem.

Data Flow Design


* With the high level description confirmed, logic equations describing the data flow are then created carry = (x AND y) AND enable result = (x'y OR xy') AND enable
x y enable

(x AND y) AND enable (x'y OR xy') AND enable

carry result

* Again, the model can be simulated at this level to confirm the logic equations

Logic Design
* Finally, a structural description is created at the gate level
x y enable x carry

result

* These gates can be pulled from a library of parts

What is VHDL?
VHDL is the VHSIC (Very High Speed Integrated Circuit) Hardware Description Language A Simulation Modeling Language

A Design Entry Language


A Standard Language A Netlist Language

History of VHDL
* 1981: Initiated in 1981 by US DoD to address the hardware life-cycle crisis

* 1983-85: Development of baseline language by Intermetrics, IBM and TI


* 1986: All rights transferred to IEEE

* 1987: Publication of IEEE Standard


* 1987: Mil Std 454 requires comprehensive VHDL descriptions to be delivered with ASICs * 1994: Revised standard (named VHDL 1076-1993)

How is VHDL used?


* For design specification * For design capture * For design simulation * For design documentation * As an alternative to schematics

* As an alternative to proprietary languages

WHY VHDL?

It will dramatically improve your productivity

Features of VHDL
* Support for concurrent statements - in actual digital systems all elements of the system are active simultaneously and perform their tasks simultaneously. * Library support - user defined and system predefined primitives reside in a library system * Sequential statements - gives software-like sequential control (e.g. case, if-then-else, loop)

Features of VHDL
* Support for design hierarchy

M M

Features of VHDL
* Generic design - generic descriptions are configurable for size, physical characteristics, timing, loading, environmental conditions. (e.g. LS, F, ALS of 7400 family are all functionally equivalent. They differ only in timing.
* Use of subprograms - the ability to define and use functions and procedures - subprograms are used for explicit type conversions, operator re-definitions, ... etc

Features of VHDL
* Type declaration and usage - a hardware description language at various levels of abstraction should not be limited to Bit or Boolean types. - VHDL allows integer, floating point, enumerate types, as well as user defined types - possibility of defining new operators for the new types.

Features of VHDL
* Timing control - ability to specify timing at all levels - clocking scheme is completely up to the user, since the language does not have an implicit clocking scheme - constructs for edge detection, delay specification, ... etc are available
* Technology independent

What about Verilog?


* Verilog has the same advantage in availability of simulation models *Verilog has a PLI that permits the ability to write parts of the code using other languages * VHDL has higher-level design management features (configuration declaration, libraries) * VHDL and Verilog are identical in function and different in syntax * No one can decide which language is better.

VHDL Design Process

Entity

Architecture 1 (behavioral)

Architecture 2 (dataflow)

Architecture 3 (structural)

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