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Resolution Functions

The document discusses the difference between std_logic and std_ulogic types in VHDL. Std_ulogic is an unresolved type without a resolution function, while std_logic is a resolved type with an associated resolution function that determines how multiple drivers are resolved. Resolution functions take a vector of the parent type as input and return the resolved value, allowing for modeling of buses with multiple drivers.

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Shabir Parah
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242 views

Resolution Functions

The document discusses the difference between std_logic and std_ulogic types in VHDL. Std_ulogic is an unresolved type without a resolution function, while std_logic is a resolved type with an associated resolution function that determines how multiple drivers are resolved. Resolution functions take a vector of the parent type as input and return the resolved value, allowing for modeling of buses with multiple drivers.

Uploaded by

Shabir Parah
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Reconfigurable Computing Resolution Functions

John Morris
Chung-Ang University The University of Auckland

Iolanthe at 13 knots on Cockburn Sound, Western Australia

Whats the difference between

std_logic and std_ulogic?


The library ieee.std_logic_1164 has two types

std_logic and std_ulogic


To understand the difference, consider this circuit

where the blue signal line has more than one driver attached to it? (eg its a bus) How do we set up our model so that the simulator knows the rules? ie which signal overrides the others or how the signals combine together

Contending drivers
Remember that VHDL knows nothing about the IEEE 1164 rules To VHDL, the only primitive operations are those of a normal programming language
addition, subtraction, etc assignment It does distinguish between signal and variable assignment, but only with respect to the timing of assignment of new values!

ieee.std_logic_1164 is NOT part of the VHDL standard So when two std_logic values are applied to the same signal (ie wire), a VHDL simulator has to know that
1 overrides Z, U, X, H, L, 1 and 0 lead to X etc

Unresolved signals
std_ulogic is an unresolved type It is an error to define a model in which two drivers can set the value of an unresolved signal because there is no resolution function associated with the signal that can be invoked to determine which driver overrides the other It is defined simply:
TYPE std_ulogic IS (U,X,0,1,Z,W,L,H,-);

ie it is an enumerated type with possible values: U, This says nothing about the behaviour of std_ulogic signals
Their behaviour is encoded in the functions (and, or, ) that take std_ulogic arguments

On the other hand, std_logic is an resolved type

Unresolved signals
On the other hand, std_logic is an resolved type

It is defined:
(see maxplus2\vhdl93\ieee\std1164.vhd)

SUBTYPE std_logic IS resolved std_ulogic; Note that there is a function definition just preceding this type:

FUNCTION resolved( s: std_ulogic_vector ) RETURN std_ulogic; SUBTYPE std_logic IS resolved std_ulogic;


Thus resolved is a function that takes a vector of std_ulogic elements and returns a value of std_ulogic type This function is called a resolution function It is called whenever two or more sources (signal assignments) drive a std_logic signal

Resolution functions
Any resolved signal (ie one that may be driven by two sources) is defined by a type that has a resolution function associated with it A resolved type is a subtype
It can resolve a conflict of multiple instances of the parent type

The name of the resolution function immediately precedes the name of the type being resolved FUNCTION resolved( s: std_ulogic_vector ) The resolution functions RETURN std_ulogic; argument is a vector of elements of the type being resolved SUBTYPE std_logic IS resolved std_ulogic;
The simulator will place the actual values to be resolved in this vector and call the resolution function eg with 3 drivers for a std_logic signal, the argument to resolved might be (Z, H, 1) which should return 1

return value is the parent type It will determine which of the values of the parent type result when the vector of signal values is applied

Implementation of resolution functions


The simplest way to implement a resolution function uses a table eg for std_logic (see maxplus\vhdl93\ieee\std1164b.vhd)
TYPE std_logic_table IS ARRAY(std_ulogic,std_ulogic) OF std_ulogic; CONSTANT resolution_table : std_logic_table := ( -U X 0 1 Z W L H ( U, U, U, U, U, U, U, U, U ), -- U ( U, X, X, X, X, X, X, X, X ), -- X ( U, X, 0, X, 0, 0, 0, 0, 0 ), -- 0 ( U, X, X, 1, 1, 1, 1, 1, 1 ), -- 1 ( U, X, 0, 1, Z, W, L, H, X ), -- Z );

Implementation of resolution functions


The function resolved is now very simple (see maxplus\vhdl93\ieee\std1164b.vhd)
-- On entry, s will contain the actual values being driven -- this signal FUNCTION resolved ( s: std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_logic := Z; -- default, weakest BEGIN IF ( sLENGTH = 1 ) THEN RETURN s(sLOW); ELSE FOR k IN sRANGE LOOP -- Take each signal in turn and determine the result of -- combining it with the previous result result := resolution_table(result,s(k)); END LOOP; END IF; RETURN result; END resolved;

Writing resolution functions


You may never need to! std_logic_1164 defines the most commonly needed one! But, 1. You may be using integer types instead of std_logic_vector in a model of a processor for
convenience speed in simulation

You will need to define a resolved integer types if your model has a bus with multiple drivers in it
You will need to have a convention for disconnecting a driver, eg setting a driver to emit 0 when its not driving the bus (where you would drive a Z with std_logic)
You can also explicitly disconnect a driver with VHDLs DISCONNECT statement

Resolution functions
2. You may have defined an abstract type You (correctly) dont want to be bothered with implementation details yet Your bus is a collection of signals (address, data, command, etc); you have a type for each one; so the bus itself is defined as a VHDL RECORD The synthesizer will eventually convert it to logic for you! Again you will need a resolution function 3.

Simulation speed
std_ulogic does not have a resolution function associated with it it should use less simulation time (ie run faster) than std_logic With std_logic, the simulator may end up checking for (or calling) the resolution function for every assignment std_ulogic is recommended wherever possible It may save simulation time std_logic is a subtype, so it is possible to convert between them whenever necessary res_signal <= std_logic(unres_signal);

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