Verilog HDL Tutorial
Brigette Huang - Autumn
08/03/25 2002 1
Tutorial Outline
• Introduction
• Circuit Modeling
• Gate-level Modeling
• Data-level Modeling
• Behavioral Modeling
• Testing & Simulation
Brigette Huang - Autumn
08/03/25 2002 2
Introduction
• What is Verilog HDL?
Verilog HDL is a Hardware Description
Language that can be used to model a
digital system at many levels of
abstraction:
– Algorithmic-level
– Gate-level
– Switch-level
Brigette Huang - Autumn
08/03/25 2002 3
Where can we use Verilog HDL?
• Verilog is designed for circuit verification and
simulation, for timing analysis, for test
analysis (testability analysis and fault
grading) and for logic synthesis.
• For example, before you get to the structural
level of your design, you want to make sure
the logical paths of your design is faultless
and meets the spec.
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Basic Procedure of Using Verilogger
• Install Verilog.
• http://bleyer.org/icarus/
• https://www.referencedesigner.com/tutorials/verilog/verilog_01.p
hp
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Basic Syntax of a Module
Module module_name (port_list);
Declarations:
input, output, wire, parameter…..
System Modeling:
describe the system in gate-level, data-flow, or
behavioral style…
endmodule
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Basic Module Construction
// Compute the logical AND and OR of inputs A
and B.
AND_OR
A
andOut
TheAndGate
orOut
B
TheOrGate
module AND_OR(andOut, orOut, A, B);
output andOut, orOut;
input A, B;
and TheAndGate (andOut, A, B);
or TheOrGate (orOut, A, B);
endmodule
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08/03/25 2002 7
Gate-Level Modeling
Systems structure can be described using Build-in
gates or pre-built modules.
Basic syntax is :
gate-type #delay instance1_name(outputs.., inputs.. ),
:
:
instance6_name(outputs.., inputs.. );
pre-built module module_instance1(output…,inputs..);
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The Built-in Primitive Gates
• Multiple-input gates:
– and, nand, or, nor, xor, xnor
xor xor1(out, inA, inB, inC);
• Multiple-output gates:
– buf, not
not inverter1(fanout1, fanout2, in);
• Tristate gates:
– bufif0, bufif1, notif0, notif1
bufif0 tbuffer1(out, in, control);
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08/03/25 2002 9
Gate Delays
• Syntax: #(Tplh, Tphl)
• Examples:
nor #10 Tplh =Tphl=10 time
units
nor #(3,5) Tplh=3, Tphl=5
nor #(2:3:4, 5) Tplh=(min2,typ3,max4)
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08/03/25 2002 10
Example: A 4 to1 Multiplexer
D3 T3
D2 T2
Z
D1 T1
D0 T0
S0
S1
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Simple Example
module Mux4_1 (Z, D,S);
output Z;
input [3:0] D;
input [1:0] S;
wire S0b, S1b, T0, T1, T2, T3;
not #5 inv0(S0b, S[0]),
inv1(S1b, S[1]);
and #10 and0(T0, D[0], S1b, S0b),
and1(T1, D[1], S1b, S[0]),
and2(T2, D[2], S[1], S0b),
and3(T3, D[3], S[0], S[1]);
or #10 or1(Z, T0,T1,T2,T3);
endmodule
Brigette Huang - Autumn
08/03/25 2002 12
Data-flow Modeling
• The basic mechanism used to model a
design in the dataflow style is the
continuous assignment.
• In a continuous assignment, a value is
assigned to a net.
• Syntax:
assign #delay LHS_net = RHS_expression;
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08/03/25 2002 13
Example: 2 to 4 Decoder
Z[0]
A
Z[1]
B Z[2]
EN Z[3]
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08/03/25 2002 14
Example
module Decoder 2_4(A,B,EN,Z);
Input A,B,EN;
output [0:3] Z;
wire Ab, Bb;
assign #1 Ab=~A;
assign #1 Bb=~B;
assign #2 Z[0]=~(Ab & Bb & EN);
assign #2 Z[1]=~(Ab & B & EN);
assign #2 Z[2]=~(A & Bb & EN);
assign #2 Z[3]=~(A & B & EN);
endmodule
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08/03/25 2002 15
Behavioral Modeling
• The behavior of a design is described
using procedural constructs. These are:
– Initial statement: This statement executes
only once.
– Always statement: this statement always
executes in a loop forever…..
• Only register data type can be assigned
a value in either of these statements.
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Always Statement
• Syntax: always
#timing_control
procedural_statement
• Procedural statement is one of :
– Blocking Procedural_assignment
always
@ (A or B or Cin)
begin
T1=A & B;
T2=B & Cin;
T3=A & Cin;
Cout=T1 | T2 | T3;
end
T1 assignment is occurs first, then T2, then T3….
Brigette Huang - Autumn
08/03/25 2002 17
Procedural statements
Conditional_statement
always
@(posedge clk or posedge reset)
if ( Sum <60)
begin
Grade = C;
Total_C=Total_C +1;
end
else if (Sum<75)
Grade = B;
else
Grade = A;
Brigette Huang - Autumn
08/03/25 2002 18
Procedural statements
Case_statement
always
@(Time ==7)
case(Day)
Tue: Pocket-Money = 6;
Mon,
Wed: Pocket_Money = 2;
Fri,
Sat,
Sun: Pocket_Money = 7;
default: Pocket_Money= 0;
endcase
Brigette Huang - Autumn
08/03/25 2002 19
Let’s look at a file to review what
we have learned today…..
Brigette Huang - Autumn
08/03/25 2002 20
References
• Couple of good verilog books here:
– A Verilog HDL Primer by J. Bhasker
– Verilog HDL: A Guide to Digital Design and
Synthesis by Samir Palnitkar
• Special thanks to
Professor Peckol and Professor Hauck for
their support and the tutorial documents
they provided…..
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08/03/25 2002 21
