Computer Organization

Lecture IV
Presented by Tandoh Lawrence (PhD)
REVISION
• What do we call the manipulation of Boolean variables/values?
• What are the basic operations in Boolean algebra?
• There are two ways of representing Boolean operations, what are
they?
• What do each of these stand for?
Additional information
• Logic gates are used in designing digital circuits
• These circuits can be divided into:
• Decision structures
• Storage structures
• We will tackle the former first
• Decision structures can be used to implement the addition and subtraction (in one’s or
two’s complement) that we studied
• Half adder
• Full adder
• Decision structures can also be purely decisional
• Decoder
• Multiplexer
• Programmable logic array
 Digital circuits
• As mentioned before, digital circuits are made up of logic gates
• How can we transform the theoretical addition and subtraction that we studied into a digital circuit
• Can be done using combinational circuits
• The output of combinational circuit at any instant of time, depends only on the levels present at input terminals.
• The combinational circuit do not use any memory. The previous state of input does not have any effect on the
present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.
Implementing addition and
subtraction using logic gates
• Both addition and subtraction will be implemented using addition
because of one’s and two’s components
• Full adder = main component of our implementation
• Derived from half adder
• Steps for implementation
• Generate the truth table for the operation
• Translate the truth table into a Karnaugh map
• Further simplify the expression obtained from the Karnaugh map if possible
with the aid of laws of Boolean algebra
• Convert the final expression into a logic gate diagram
Generating truth tables
• These are tables showing the possible combinations of
all inputs and their corresponding outputs
• The total number of rows in this table is 2n where n = Truth table for
number of inputs binary addition
• Rules for creating a truth table
• ½ of the elements in the first column are set to 0 whilst the
rest are set to one
• The next column is filled with iterating patters of 0’s and 1’s
• Each pattern will have ¼ elements set to 0’s and ¼ elements set to 1’s
• The pattern for each subsequent column is (previous column)2
• Each of the outputs are computed using rules of Boolean
algebra
Karnaugh maps (K-maps)
• K-maps help us to identify the gates that will make up our digital circuits
• Expressions obtained from them are not necessarily optimal and can be
further simplified using laws of Boolean algebra
• How to create and use K-maps
• Create a table for 2,3, or 4 elements (more are possible but difficulty increases with
an increasing number of elements)
• Variable distribution is done in the following manner:
• A\B, A\BC, AB\CD
• Numbering of cells is done in the following manner:
• 0,1
• 0,1\00,01,11,10
• 00,01,11,10\00,01,11,10
Karnaugh maps (K-maps)
• For each variable combination insert a 1 or a 0 as seen in the truth table
• Search for groups of one’s (1’s)
• These groups should consist of powers of 2’s: i.e. 1,2,4,8,…
• Each element that corresponds to a 0 is set to a NOT value
• Each element that corresponds to a 1 is set to its original value
• The result of each grouping is a product
• For each grouping search for elements that don’t change and use them to
build the Boolean expression
• Note that K-maps allow overlapping of groups
• Solve example for binary addition with half adder as well as an example with
groupings
Laws of Boolean algebra
These can be considered as identities that help us to simplify Boolean
expressions
Description Expression

A+1=1 Annulment A+ =1 Complement NULL 0

IDENTITY 1
A+0=A Identity A. =0 Complement Input A A

Input B B

A.1=A Identity NOT A

A+B = B+A Commutative
NOT B

A.0=0 Annulment A AND B (AND) A.B

A.B = B.A Commutative
A AND NOT B A.

NOT A AND B .B
A+A=A Idempotent
= de Morgan’s Theorem NOT AND (NAND)

A OR B (OR) A+B
A.A=A Idempotent
A OR NOT B A+

= de Morgan’s Theorem NOT A OR B +B

NOT = A Double Negation
NOT OR (NOR)

Exclusive-OR A. + .B

Exclusive-NOR A.B+ .
An example was seen in the half adder Karnaugh maps and another will be given in
the full adder logic gate Karnaugh map
Half adder
• Binary addition of two bits is implemented using the half adder
• This adder takes two bits as inputs (A, B) and produces two outputs
• Sum (S)
• Carry (C)
• Is not suitable for implementation of addition of several (n) bits because of the absence of a carry in
input
• The truth table and the Karnaugh map for this adder have already been discussed so we will just
present the logic circuit diagram here
Full adder I
• In order to be able to add “n” bits together, our adder must support a carry in bit
• The full adder addresses that issue
• Takes as input three values (A, B, Carry in (Cin)) and generates two outputs (Sum (S),
Carry out (Co))
• Discuss how the full adder logic gate circuit is generated
• Different variants of the circuits exist with some being more efficient than the others
• Different versions and levels of efficiency are due to the amount of simplification
done using laws of Boolean logic
Full adder II
• The previously described full adder can
only add two bits and considers carry
• To add inputs of “n” bits each we must
employ an “n” bit parallel adder also
called a ripple carry adder
• The 4-bit parallel adder is the most
common example of this
Logic gates for subtraction
• We will be considering one’s and two’s
complement subtraction
• These can be easily implemented using full
adders in addition to a few other logic gates
• Note that there will be a separate diagram for
each of the scenarios of both one’s and two’s
complement
• Discuss the half and full adder for each of the
scenarios of the ones and twos complement
Other logic gates under
combinational logic
• There are other logic circuits that fall under the combinational logic
that do not include circuits that implement arithmetic
• These circuits are
• Decoders
• Multiplexers
• Programmable logic arrays
• These combinational logic circuits generally have fixed structures and
therefore we will only study these without going into further details
Decoders overview
• a logic circuit that converts a coded input to a “decoded” output by converting the input
into a different format
• Binary decoders can be used to:
• Convert BCD/binary value into “denary format”, “octal format” or “hexadecimal format”
• Decoding the opcode of an instruction (Decode stage of the FDE Cycle)
• An “n” input decoder can have a maximum of 2n outputs
• Input will thus always be higher than output
• Usually however, the maximum number of outputs is used
• Usually, the value of the “ith” output node is one if the value of the n-bit input is “i” whilst
the output on all other nodes is zero
• There are four popular decoders: 2-to-4 decoder, 3-to-8 decoder and 4-to-16 decoder
• We will only consider the first two
2-to-4 binary decoder
• this decoder has 2 inputs and 4 outputs
• The truth table, block and logic gate diagram for the decoder are shown below
• Can be used to convert binary numbers (0-3) into denary
3-to-8 binary decoder
• this decoder has 3 inputs and 8 outputs
• Structure is very similar to the 2-to-4 binary decoder
• The truth table, block and logic gate diagram for the decoder are
shown below
• Can be used to convert binary numbers (0-7) into octal
Multiplexers overview
• Multiplexers are also known as MUX’s
• Accept “n” inputs and return a single (1) output
• Employ the use of select lines that have states and are used to determine
which input is forwarded to the output line
• There exists a relationship between the number of input lines “n” and the
number of select lines “m”
• 2m = n
• Hence:
• For 2 input lines m = 1
• For 4 input lines m = 2
• For 8 input lines m = 3 and so on
• In summary, a multiplexer has “n” input lines, 2m select lines and a single
output line
• Used for:
• Conversion
• Selecting a single output from several
• Converting parallel signals into serial for transmission over a single line
• Implementing a scheduler which determines which tasks in a pool should be
executed first
How the multiplexer works I
• On the inside the MUX works by simply deciding based on the value
of the select line(s) which (one) of the inputs should be connected to
the output
• Popular examples of MUX’s include 2-to-1, 4-to-1, and 8-to-1
• Just as it is the case with all logic circuits, multiplexers can also be
designed using the standard design process to which we have been
introduced
• Let us consider the design of the simplest multiplexer 2-to-1
How the multiplexer works II
(design of 2-to-1 multiplexer)
• Below we present the truth table, K-map and logic circuit diagram for a 2-to-1 multiplexer
• In this multiplexer, input “A”/I0 is transferred to the output (Y) when the select value (S) is
“0” and the “B”/I1 input value is transferred to the output when the select has a state of
“1”
Select (S) A B Output (Y) S\AB 00 01 11 10
0 0 0 0 0 0 0 1 1
0 0 1 0 1 0 1 1 0
0 1 0 1
0 1 1 1 Sum of products =
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Beyond the 2-to-1 MUX
• The situation becomes more complex with multiplexers that have a larger number
of inputs
• The design process however remains the same
• Note that the number of select lines will increase with an increasing number of
inputs based on given relation
• Note that the output of the multiplexer will solely depend on the states of the
select lines
• For example, lets consider a 4-to-1 multiplexer with inputs (A, B, C, and D) which
will have a total of 2 select lines since 22 = 4
• When S1S2 = 00 output will be “A”
• When S1S2 = 01 output will be “B”
• When S1S2 = 10 output will be “C”
• When S1S2 = 11 output will be “D”
Programmable logic array (PLA)
• Digital circuits that consist of an array of and gates and an array of AND
gates followed by an array of OR gates
• Both the AND and OR gates are programmable
• During the design of the integrated circuit (IC) it has no specific purpose
• Purpose is determined later on when the IC is coded
• Coding/programming is hardware based and does not include any
programming language
• PLA’s take in “n” inputs and return “m” outputs
• Used as a:
• Counter
• Decoder
Structure of a PLA
• Each input of the PLA consists of the actual input value as well as its complement
• The complement is implemented with the aid of a not gate
• The output of a PLA forms a sum of products just as the output of a K-map
• The AND gates form the products whilst the OR gates form the sum
• Below is a block diagram and a logic circuit for a PLA