CSC 315:

Computer
Organization and
Architecture
Chapter (3
3: A Top-Level View of Computer
Function and Interconnection.
Units)
Dr. Asunogie 1
EDO STATE UNIVERSITY UZAIRUE (EDSU)
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The reasoning behind these concepts is that there is a small set of basic
logic components that can be combined in various ways to store binary
data and perform arithmetic and logical operations on that data. If
there is a particular computation to be performed, a configuration of
logic components designed specifically for that computation could be
constructed. We can think of the process of connecting the various
components in the desired configuration as a form of programming.
The resulting “program” is in the form of hardware and is termed a
hardwired program.

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(Figure 1)
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• Now consider this alternative. Suppose we construct a general-purpose
configuration of arithmetic and logic functions. This set of hardware will perform
various functions on data depending on control signals applied to the hardware.
• In the original case of customized hardware, the system accepts data and produces
results (Figure 1a). With general-purpose hardware, the system accepts data and
control signals and produces results. Thus, instead of rewiring the hardware for
each new program, the programmer merely needs to supply a new set of control
signals.
• The entire program is actually a sequence of steps. At each step, some arithmetic
or logical operation is performed on some data. For each step, a new set of control
signals is needed. The instruction interpreter is a unique code for each possible set
of control signals, see it added add to the general-purpose hardware segment it
that can accept a code and generate control signals as shown in Figure 1b
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• Programming is now much easier. Instead of rewiring the hardware for each new
program, all we need to do is provide a new sequence of codes. Each code is, in
effect, an instruction, and part of the hardware that interprets each instruction and
generates control signals. To distinguish this new method of programming, a
sequence of codes or instructions is called software.
• Figure1b indicates two major components of the system: an instruction interpreter
and a module of general-purpose arithmetic and logic functions. These two
constitute the CPU. Several other components are needed to yield a functioning
computer. Data and instructions must be put into the system. For this we need some
sort of input module. This module contains basic components for accepting data and
instructions in some form and converting them into an internal form of signals that
is usable by the system. A means of reporting results is needed, and this is in the
form of an output module. Taken together, these are referred to as I/O components.
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• One more component is needed. An input device will bring instructions and data in sequentially.
But a program is not invariably executed sequentially; it may jump around (e.g., the IAS jump
instruction). Similarly, operations on data may require access to more than just one element at a
time in a predetermined sequence.
• Hence, there must be a place to store temporarily both instructions and data. That module is
called memory, or main memory, to distinguish it from external storage or peripheral devices.
Von Neumann pointed out that the same memory could be used to store both instructions and
data.
• The CPU exchanges data with memory. For this purpose, it typically makes use of two internal (to
the CPU) registers: a memory address register (MAR), which specifies the address in memory for
the next read or write, and a memory buffer register (MBR), which contains the data to be
written into memory or receives the data read from memory. Similarly, an I/O address register
(I/OAR) specifies a particular I/O device. An I/O buffer (I/OBR) register is used for the exchange of
• data between an I/O module and the CPU.

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(Figure 2)
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Memory module and input/output
module
• Figure 2 illustrates these top-level components and suggests the
interactions among them.
• A memory module consists of a set of locations, defined by
sequentially numbered addresses. Each location contains a binary
number that can be interpreted as either an instruction or data.
• An I/O module transfers data from external devices to CPU and
memory, and vice versa. It contains internal buffers for temporarily
holding these data until they can be sent on.

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(Figure 3)
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• At the beginning of each instruction cycle, the processor fetches an instruction from
memory. In a typical processor, a register called the program counter (PC) holds the
address of the instruction to be fetched next. Unless told otherwise, the processor always
increments the PC after each instruction fetch so that it will fetch the next instruction in
sequence (i.e., the instruction located at the next higher memory address).
• So, for example, consider a computer in which each instruction occupies one 16-bit word
of memory. Assume that the program counter is set to memory location 300, where the
location address refers to a 16-bit word. The processor will next fetch the instruction at
location 300. On succeeding the instruction cycles, it will fetch instructions from locations
301, 302, 303, and so on. This sequence may be altered, as explained presently.
• The fetched instruction is loaded into a register in the processor known as
• the instruction register (IR). The instruction contains bits that specify the action the
processor is to take. The processor interprets the instruction and performs the required
action.
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• In general, these actions fall into four categories:
• Processor-memory: Data may be transferred from processor to memory or from memory
to processor.
• Processor-I/O: Data may be transferred to or from a peripheral device by transferring
between the processor and an I/O module.
• Data processing: The processor may perform some arithmetic or logic operation on data.
• Control: An instruction may specify that the sequence of execution be altered. For
example, the processor may fetch an instruction from location 149, which specifies that
the next instruction be from location 182. The processor will remember this fact by
setting the program counter to 182. Thus, on the next fetch cycle, the instruction will be
fetched from location 182 rather than 150.
• An instruction’s execution may involve a combination of these actions.

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(Figure 4)
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• Consider a simple example using a hypothetical machine that includes
the characteristics listed in Figure 4. The processor contains a single
data register,
• called an accumulator (AC). Both instructions and data are 16 bits
long. Thus, it is
• convenient to organize memory using 16-bit words. The instruction
format provides
• 4 bits for the opcode, so that there can be as many as 24 = 16
different opcodes, and
• up to 212 = 4096 (4K) words of memory can be directly addressed.
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• Figure 5 illustrates a partial program execution, showing the relevant portions of memory and processor registers.
The program fragment shown adds the contents of the memory word at address 940 to the contents of the
memory word at address 941 and stores the result in the latter location. Three instructions, which can be
described as three fetch and three execute cycles, are required:
• 1. The PC contains 300, the address of the first instruction. This instruction (the value 1940 in hexadecimal) is
loaded into the instruction register IR, and the PC is incremented. Note that this process involves the use of a
memory address register and a memory buffer register. For simplicity, these intermediate
• registers are ignored.
• 2. The first 4 bits (first hexadecimal digit) in the IR indicate that the AC is to be loaded. The remaining 12 bits (three
hexadecimal digits) specify the address (940) from which data are to be loaded.
• 3. The next instruction (5941) is fetched from location 301, and the PC is incremented.
• 4. The old contents of the AC and the contents of location 941 are added, and the result is stored in the AC.
• 5. The next instruction (2941) is fetched from location 302, and the PC is incremented.
• 6. The contents of the AC are stored in location 941.
• In this example, three instruction cycles, each consisting of a fetch cycle and an execute cycle, are needed to add
the contents of location 940 to the contents of 941.
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Figure 6
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• The execution cycle for a particular instruction may involve more than one reference to memory. Also, instead
of memory references, an instruction may specify an I/O operation. With these additional considerations in
mind, Figure 6 provides a more detailed look at the basic instruction cycle of Figure 3.
• For any given instruction cycle, some states may be null and
• others may be visited more than once. The states can be:
• Instruction address calculation (IAC): Determine the address of the next instruction to be executed. Usually,
this involves adding a fixed number to the address of the previous instruction.
• Instruction fetch (IF): Read instruction from its memory location into the processor.
• Instruction operation decoding (IOD): Analyze instruction to determine type of operation to be performed
and operand(s) to be used.
• Operand address calculation (OAC): If the operation involves reference to an operand in memory or available
via I/O, then determine the address of the operand.
• Operand fetch (OF): Fetch the operand from memory or read it in from I/O.
• Data operation (DO): Perform the operation indicated in the instruction.
• Operand store (OS): Write the result into memory or out to I/O.
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• Virtually all computers provide a mechanism by which other modules
(I/O, memory) may interrupt the normal processing of the processor.
Table 1 lists the most common classes of interrupts. The specific
nature of these interrupts is examined
• However, we need to introduce the concept
• now to understand more clearly the nature of the instruction cycle
and the implications of interrupts on the interconnection structure.

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Figure 7
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Figure 8
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• From the point of view of the user program, an interrupt is just that:
an interruption of the normal sequence of execution. When the
interrupt processing is completed,
• execution resumes (Figure8). Thus, the user program does not have to
contain any special code to accommodate interrupts; the processor
and the operating system are
• responsible for suspending the user program and then resuming it at
the same point.

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Figure 9

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• To accommodate interrupts, an interrupt cycle is added to the instruction cycle, as shown
in Figure 9. In the interrupt cycle, the processor checks to see if any interrupts have
occurred, indicated by the presence of an interrupt signal. If no interrupts are pending,
the processor proceeds to the fetch cycle and fetches the next instruction of the current
program. If an interrupt is pending, the processor does the following:
• • It suspends execution of the current program being executed and saves its context. This
means saving the address of the next instruction to be executed and any other data
relevant to the processor’s current activity.
• • It sets the program counter to the starting address of an interrupt handler routine.
• The processor now proceeds to the fetch cycle and fetches the first instruction in the
interrupt handler program, which will service the interrupt. The interrupt handler
program is generally part of the operating system. Typically, this program
• determines the nature of the interrupt and performs whatever actions are needed.
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Figure 10

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• To appreciate the gain in efficiency, consider Figure 10, which is a timing
diagram based on the flow of control in Figures 7a and 7b. In this figure, user
program code segments are shaded green, and I/O program code segments
are shaded gray. Figure 10a shows the case in which interrupts are not used.
The processor must wait while an I/O operation is performed.
• Figures 7b and 10b assume that the time required for the I/O operation is
relatively short: less than the time to complete the execution of instructions
between write operations in the user program. In this case, the segment of
code labeled code segment 2 is interrupted. A portion of the code (2a)
executes (while the I/O operation is performed) and then the interrupt occurs
(upon the completion of the I/O operation). After the interrupt is serviced,
execution resumes with the remainder of code segment 2 (2b).
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Figure 11 31
• The more typical case, especially for a slow device such as a printer, is that the
I/O operation will take much more time than executing a sequence of user
instructions.
• Figure 7c indicates this state of affairs. In this case, the user program reaches
the second WRITE call before the I/O operation spawned by the first call is
complete.
• The result is that the user program is hung up at that point. When the
preceding I/O operation is completed, this new WRITE call may be processed,
and a new I/O operation may be started. Figure 11 shows the timing for this
situation with and without the use of interrupts. We can see that there is still
a gain in efficiency because part of the time during which the I/O operation is
under way overlaps with the execution of user instructions.
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 (Figure 12)

Figure 12 shows a revised instruction cycle state

diagram that includes interrupt cycle processing.
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 Two approaches can be taken to dealing with multiple interrupts. The first
is to disable interrupts while an interrupt is being processed. A disabled
interrupt simply means that the processor can and will ignore that
interrupt request signal. If an interrupt occurs during this time, it generally
remains pending and will be checked by the processor after the processor
has enabled interrupts. Thus, when a user program is executing and an
interrupt occurs, interrupts are disabled immediately. After the interrupt
handler routine completes, interrupts are enabled before resuming the
user program, and the processor checks to see if additional interrupts
have occurred.
This approach is nice and simple, as interrupts are handled in strict
sequential order as shown in (Figure 13a).
The drawback to the preceding approach is that it does not take into
account relative priority or time-critical needs. For example, when input
arrives from the communications line, it may need to be absorbed rapidly
to make room for more input. If the first batch of input has not been
processed before the second batch arrives, data may be lost.
A second approach is to define priorities for interrupts and to allow an
interrupt of higher priority to cause a lower-priority interrupt handler to
be itself interrupted as shown in(Figure 13b).

(Figure 13) 34
An I/O module can exchange data directly with the
processor. Just as the processor can initiate a read or write
with memory, designating the address of a specific
location, the processor can also read data from or write
data to an I/O module. In this latter case, the processor
identifies a specific device that is
controlled by a particular I/O module. Thus, an instruction
sequence similar in form to that of Figure 5 could occur,
with I/O instructions rather than memory-referencing
instructions.
In some cases, it is desirable to allow I/O exchanges to
occur directly with memory. In such a case, the processor
grants to an I/O module the authority to read from or write
to memory, so that the I/O-memory transfer can occur
without tying up the processor. During such a transfer, the
I/O module issues read or write commands to memory,
relieving the processor of responsibility for the exchange.
This operation is known as direct memory access (DMA).

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 Figure 15 suggests the types of exchanges that are needed by indicating
the
major forms of input and output for each module type, they are:
Memory: Typically, a memory module will consist of N words of equal
length. Each word is assigned a unique numerical address (0, 1, …, N - 1).
A word of data can be read from or written into the memory. The nature
of the operation is indicated by read and write control signals. The
location for the operation is specified by an address.
I/O module: From an internal (to the computer system) point of view,
I/O is functionally similar to memory. There are two operations, read and
write.
Further, an I/O module may control more than one external device. We
can refer to each of the interfaces to an external device as a port and
give each a unique address (e.g., 0, 1, …, M - 1). In addition, there are
external data paths for the input and output of data with an external
device. Finally, an I/O module may be able to send interrupt signals to
the processor.
Processor: The processor reads in instructions and data, writes out data
after processing, and uses control signals to control the overall operation
of the system. It also receives interrupt signals.
(Figure 15)
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The preceding list defines the data to be exchanged.
The interconnection structure must support the
following types of transfers:
• Memory to processor: The processor reads an
instruction or a unit of data from memory.
• Processor to memory: The processor writes a unit of
data to memory.
• I/O to processor: The processor reads data from an
I/O device via an I/O module.
• Processor to I/O: The processor sends data to the I/O
device.
• I/O to or from memory: For these two cases, an I/O
module is allowed to exchange data directly with
memory, without going through the processor, using
direct memory access.

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 Bus Interconnections Pathways
Computer systems contain a number of different buses
that provide pathways between components at various
levels of the computer system hierarchy. A bus that
connects major computer components (processor,
memory, I/O) is called a system bus. The most common
computer interconnection structures are based on the
use of one or more system buses.

A system bus consists, typically, of from about fifty to

hundreds of separate lines.
The data lines provide a path for moving data among
system modules. These lines, collectively, are called the
data bus. The data bus may consist of 32, 64, 128, or
even more separate lines, the number of lines being
referred to as the width of the data bus. Because each
line can carry only 1 bit at a time, the number of lines
determines how many bits can be transferred at a time.
The width of the data bus is a key factor in determining
overall system performance. For example, if the data
bus is 32 bits wide and each instruction is 64 bits long,
then the processor must access the memory module
twice during each instruction cycle.
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The address lines are used to designate the source or
destination of the data on the data bus. For example, if the
processor wishes to read a word (8, 16, or 32 bits) of data from
memory, it puts the address of the desired word on the address
lines. Clearly, the width of the address bus determines the
maximum possible memory capacity of the system.
Furthermore, the address lines are generally also used to
address I/O ports. Typically, the higher-order bits are used to
select a particular module on the bus, and the lower-order bits
select a memory location or I/O port within the module. For
example, on an 8-bit address bus, address 01111111 and
below might reference locations in a memory module (module
0) with 128 words of memory, and address 10000000 and
above refer to devices attached to an I/O module (module 1).

The control lines are used to control the access to and the use
of the data and address lines. Because the data and address
lines are shared by all components, there must be a means of
controlling their use. Control signals transmit both command
and timing information among system modules. Timing signals
indicate the validity of data and address information.
Command signals specify operations to be performed.
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 Each line is assigned a particular meaning or function.
Although there are many different bus designs, on any bus
the lines can be classified into three functional groups as
shown in (Figure 16): data, address, and control lines. In
addition, there may be power distribution lines that supply
power to the attached modules.
The operation of the bus is as follows. If one module wishes
to send data to another, it must do two things: (1) obtain the
use of the bus, and (2) transfer data via the bus. If one
module wishes to request data from another module, it
must (1) obtain the use of the bus, and (2) transfer a request
to the other module over the appropriate control and
address lines. It must then wait for that second module to
send the data.
(Figure 16)

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