Unit III

•Timing and Interrupts:

•Bus timing,
•READY and wait state,
•Basic Interrupt Processing,
•Hardware Interrupts
Memory, I/O and Peripheral Interfacing: Address decoding, memory interfacing for
8086, I/O port address decoding, Study of 8255 PPI and related programs (LED and
switch interface, DAC, Stepper motor)
Pins Function

AD15 – AD0 These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15
carries higher order byte data. During the first clock cycle, it carries 16-bit address a
after that it carries 16-bit data.

A16 – A19 These are the 4 address/status buses. During the first clock cycle, it carries 4-bit
address and later it carries status signals.

Vcc It uses 5V DC supply at VCC pin 40

GND These are ground at VSS pin 1 and 20.

Clock Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MH

S7/BHE BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the
transfer of data using data bus D8-D15. This signal is low during the first clock cycle,
thereafter it is active.

Read(RD) It is available at pin 32 and is used to read signal for Read operation.

𝐑𝐞𝐚𝐝𝐲 It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is
ready to transfer data. When it is low, it indicates wait state.

RESET It is available at pin 21 and is used to restart the execution. It causes the processor t
immediately terminate its present activity. This signal is active high for the first 4 clo
cycles to RESET the microprocessor.
LE It stands for address enable latch and is available at pin
25. A positive pulse is generated each time the processor
begins any operation. This signal indicates the availability
of a valid address on the address/data lines.

DEN It stands for Data Enable and is available at pin 26. It is

used to enable Transreceiver 8286. The transreceiver is a
device used to separate data from the address/data bus.

DT/R It stands for Data Transmit/Receive signal and is available

at pin 27. It decides the direction of data flow through the
transreceiver. When it is high, data is transmitted out and
vice-a-versa.

M/IO This signal is used to distinguish between memory and I/O

operations. When it is high, it indicates I/O operation and
when it is low indicating the memory operation. It is
available at pin 28.

WR It stands for write signal and is available at pin 29. It is

used to write the data into the memory or the output
QS1 and QS0 These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction
queue.

S0, S1, S2 These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to
generate memory & I/O control signals. These are available at pin 26, 27, and 28.

LOCK When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus. It is
activated using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0 These are the Request/Grant signals used by the other processors requesting the CPU to release the system bus.
When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
here are some conditions for
QS0 and QS1. These
conditions are as follows.
S0 QS1 Status

0 0 No operation

0 1 First byte of opcode

from the queue

1 0 Empty the queue

1 1 Subsequent byte
from the queue
2 S1 S0 Status

0 0 0 Interrupt acknowledgement

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write
Explanation in steps:
1.When the processor is ready to initiate the bus
cycle , it applies a pulse to ALE during T1. Before
the falling edge of ALE, address , BHE’, DEN’, and
DT/R’ must be stable, i.e DEN = high, DT/R’ =0 for
input or 1 for output
2.During T2 address signals are disabled and S3 –
S7 are available on the AD16/S3 – AD19/S7 and
BHE’/S7.DEN’ = 0 to enable the transceiver.
3.For input operation, RD’ is active during T2 and
AD0 to AD15 go high impedance for input
4. If memory or I/O interface can perform the
transfer immediately , there is no wait state and
data is output on the bus during T3.
5. After the data is accepted by the processor, RD’
is raised high at the beginning of T4
6. For the output operation ,processor applies WR’
=0 and then the data on the data bus during T2.
7. In T4 WR’ is raised high and data signal are
disabled.
UNIT – IV
1.Basic Interrupt Processing, Hardware Interrupts.
1. Explain the purpose of Interrupts
2. Explain hardware interrupts of 8086 microprocessor.
3. Explain software interrupts of 8086 microprocessor.
4. With a neat circuit explain the NMI interrupt activation for AC
power failure.
5. Explain the operation of software interrupt instructions INT, INTO,
INT 3, and BOUND
6. Differentiate between INTR and NMI.
7. Explain INTR and INTA with timing diagram.
8. Explain power failure detection circuit using NMI interrupt
9. Explain the action taken by 8086 microprocessor when an
interrupt occurs. Explain the interrupt vector table
•The Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices
at relatively low data transfer rates, such as
keyboard inputs
• Interrupt processing allows the processor to
execute other software while the keyboard
operator is thinking about what to type next.
• When a key is pressed, the keyboard encoder
debounces the switch and puts out one pulse that
interrupts the microprocessor.
•Interrupts
• Intel processors include two hardware pins (INTR and
NMI) that request interrupts…
A hardware pin (INTA) to acknowledge the interrupt
requested through INTR.
• Flag bits IF (interrupt flag) and TF (trap flag), are also
used with the interrupt structure and special return
instruction IRET
•Interrupt can divide to five groupe:
1. hardware interrupt
2. Non-maskable interrupt
3. Software interrupt
4. Internal interrupt
5. Reset
•Intel Dedicated Interrupts
1.Type 0 The divide error whenever the result from
a division overflows or an attempt is made to
divide by zero.

2.Type 1 Single-step or trap occurs after execution

of each instruction if the trap (TF) flag bit is set.
– upon accepting this interrupt, TF bit is cleared so
the interrupt service procedure executes at full
speed
3. Type 2 The non-maskable interrupt occurs
when a logic 1 is placed on the NMI input pin to
the microprocessor.
– non-maskable—it cannot be disabled

4. Type 3 A special one-byte instruction (INT 3)

that uses this vector to access its interrupt-
service procedure.
– often used to store a breakpoint in a program
for debugging
•Type 4 Overflow is a special vector used with
the INTO instruction.
The INTO instruction interrupts the program if
an overflow condition exists. – as reflected by
the overflow flag (OF)
Operation of a Real Mode interrupt
At the end of each instruction cycle, the 8086
checks to see if any interrupts have been
requested, the 8086 responds to the interrupt by
–1. Flag register contents are pushed on the stack
–2. Interrupt (IF) & trap (TF) flags clear, disabling the
INTR pin and trap or single-step feature
–3. Contents of the code segment register (CS)are
pushed onto the stack
–4. Contents of the instruction pointer (IP) are pushed
onto the stack
–5. Interrupt vector contents are fetched and placed
into IP and CS so the next instruction executes at the
interrupt service procedure addressed by the vector
The microprocessor has two hardware interrupt inputs:
Non-maskable interrupt (NMI) and interrupt request (INTR).

Whenever the NMI input is activated, a type 2 interrupt (Single-step or trap if the trap (TF) flag bit is
set). occurs because NMI is internally decoded.
The INTR input must be externally decoded to select a vector.

ny interrupt vector can be chosen for the INTR pin, but usually use an interrupt type
number between 20H and FFH.

he INTA signal is also an interrupt pin on the microprocessor,

but it is an output that is used in response to the INTR input to apply a vector type
number to the data bus connections D7–D0. Figure 12–5 shows the three user
interrupt connections on the microprocessor.
Hardware Interrupt Request Pin (INTR )
 he non-maskable interrupt (NMI) is an edge-triggered input that
requests an interrupt
On the positive edge (0-to-1 transition).
After a positive edge, the NMI pin must remain a logic 1 until it is recognized by the
microprocessor.
The NMI input is often used for parity errors and other major system faults, such as
power failures.
Power failures are easily detected by monitoring the AC power line and causing an
NMI interrupt whenever AC power drops out.
In response to this type of interrupt, the microprocessor stores all of the internal
register in a battery-backed-up memory or an EEPROM.
Figure 12–6 shows a power failure detection circuit that provides a logic 1 to the NMI
input whenever AC power is interrupted.
In this circuit, an optical isolator provides isolation from the AC power line.
The output of the isolator is shaped by a Schmitt-trigger inverter that provides a 60
Hz pulse to the trigger input of the 74LS122 retriggerable, monostable multivibrator.
The values of R and C are chosen so that the 74LS122 has an active pulse width of 33
ms or 2 AC input periods.
Because the 74LS122 is retriggerable, as long as AC power is
applied, the Q output remains triggered at a logic 1 and remains a
logic 0. ]
If the AC power fails, the 74LS122 no longer receives trigger
pulses from the 74ALS14, which means that Q becomes a logic 0
and becomes a logic 1, interrupting the microprocessor through
the NMI pin.
The interrupt service procedure, stores the contents of all internal
registers and other data into a battery-backed-up memory. This
system assumes that the system power supply has a large enough
filter capacitor to provide energy for at least 75 ms after the AC
power ceases.
UNIT 4
Memory, I/O and Peripheral Interfacing:
Address decoding,
memory interfacing for 8086,
I/O port address decoding,
Study of 8255 PPI and related programs
SELECTION CONNECTION
RAM has CS’ and ROM has CE’ these 2 pins are low memory device
performs a reads and write operation.
Control inputs :
ROM :  OUTPUT ENABLE OC’ OR GATE G:which allows data to flow output
pins of ROM .
If OE’ AND CE’ ARE ACTIVE ,, THE OUTPUT IS ENABLE
IF OE’ IS INACTIVE , THEN OUTPUT PINS ARE DISABLED
RAM has three control signal
The output enable signal OE’ allows the selected data value
be driven on the data bus.
Chip Enable CE’ which is used to address or select this
particular memory chip
The WRITE ENABLE signal WE’, which, when set low,
indicates that you are writing to the RAM chip.
OE’ must be active to perform read operation

Memory devices have address inputs to

1.Select a memory location within the device.
2.Almost always labeled from A0, the least significant
address input, to An

here subscript n can be any value

lways labeled as one less than total number of address

pins
3.A memory device with 10 address pins has its address
pins labeled from A to A .
Address bus:10 bit Address Space:1 Kbytes
(210)
Address bus:11 bit Address Space:2 Kbytes
(211)
Address bus:16 bit Address Space:64 KBytes
(216)
Address bus:20 bit Address Space:1 Mbytes
Address bus:32 bit Address Space:4 GBytes
Address bus:34 bit Address Space:16GBytes
Address bus:36 bit Address Space:64GBytes
Address bus:38 bit Address Space:256GBytes

 If 64kbyte EPROM
Then 2^6 1Kbyte= 2^6 x 2^10 = 2^16 byte
therefore for 64KB= address line is 16
 If 32kbyte EPROM
An 8-bit-wide memory device is often called a byte-wide
memory.

ost devices are currently 8 bits wide

Memory devices often refer to memory locations times bits per
location.
A
memory device with 1K memory locations and 8
bits in each location

t is often listed as a 1K  8

1K

8 bits
 ADDRESS DECODING
WHY Decoding of address is necessary
― to attach a memory device to the microprocessor.
― It allows the microprocessor to address a single
address within a block of Memory or Input/ Output.
―It can access the data stored in the memory by
specifying its address

―In 8086 has 20 address lines connections and the

2716 EPROM has 11 connections.
―The 8086 sends out a 20-bit memory address
whenever it reads or writes data
―Because the 2716 has only 11 address pins,
there is a mismatch that must be corrected
―The decoder corrects the mismatch by decoding
address pins that do not connect to the memory
component.
00000H RAM

FFFFFH EROM
1. Design an 8086 based system to interface with
2K byte EPROM. Use NAND gate for address
decoding. Memory Map 2K x 8 EPROM
C B A
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
FF800H -TO
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FFFFFH

( using calc to find no. of lines ln2000/ln2 = 10.9

=11 address lines) i.e A10 to A0
The remaining nine address pins (A19–A11).
The decoder selects the EPROM from one of the
 Cont’d simple NAND gate decoder
When the 2K × 8 EPROM is used,
address connections A10 to A1 of the 8086 are connected
to address inputs A10 to A0 of the EPROM.
Decoding
The remaining nine address pins (A19–A11) are connected to
the inputs of a NAND gate decoder
In this circuit a NAND gate decodes the memory
address
In this circuit , whenever the 8086 address pins attached
to its input are logic are’1’.
Output of NAND gate is logic ‘0’
The active low output of NAND gate decoder is connected
to Chip enable(CE) input pin  enables the EPROM
The output enable OE pin is activated by the 8086 RD
signal
When chip enable pin and output enable pin is logic
0
Then EPROM will read the data
 Cont’d simple NAND gate decoder
If the 20-bit binary address, decoded by the
NAND gate, is written so that the leftmost nine
bits( A19- A11) are 1s
and the rightmost 11 bits (A0- A10) are don’t
cares (X), the actual address range of the
EPROM can be determined.
don’t care is a logic 1 or a logic 0, whichever is
appropriate

xample:

111 1111 1xxx xxxx xxxx

111 1111 1000 0000 0000 (FF800H) to

111 1111 1111 1111 1111(FFFFFH)--

The(211 ) 2K EPROM is decoded at memory address
locations FF800H–FFFFFH
The 3-to-8 Line Decoder Knowledge of IC
(74LS138)
a common integrated
circuit decoder found in
many systems is the
74LS138 3-to-8 line
decoder.
 Knowledge of IC
The truth table shows that only one of the
eight outputs ever goes low at any time.
To be active, the G2A and G2B inputs must
both be low (logic 0), and G1 must be high
(logic 1).

For any of the decoder’s outputs to go low, the

three enable inputs (G2A ,G2B , and G1) must
all be active.

Once the 74LS138 is enabled, the address

inputs (C, B, and A) select which output pin
goes low.
 2. Design an 8086 based system to
interface that uses eight 2764 EPROMs
(8K x 8)for a 64K  8 section of memory .
Sample Decoder Circuit: illustrated in Figure 10–15
The outputs of the decoder are connected to eight different 2764
EPROM memory devices.
Here, the decoder selects eight 8Kbyte blocks of memory for a total
memory capacity of 64K bytes

It is know the EPROM ends at FFFFFH

find the starting address

hen the 8K × 8 EPROM is used

23 x 1K = 23 x 210 = 213 B

equired EPROM is 64KB hence 8KB eight is required

 Therefore address lines required is13 line i.e A12 to A0
 A19 toA13 are connected to 3-8 line decoder.
 CBA=000 Frist 8K × 8 EPROM is used
C B A
A A A A A A A A A A A A A A A A A A A A
1 1 1 16 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
9 8 7 5 4 3 2 1 0
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
F0000H -TO F1FFFH
1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
F2000H to F3FFFH
 ABC are input select lines which are connected to
A13,A14,A15
 G1= Input G1 is connected directly to A16.
 G2B: When all three address inputs (A17 A18 A19) are high, the
output of this NAND gate goes low and enables input G2B of
the 74LS138.
 G2A is grounded.
 EPROM

DECODER

Select lines

Enable
Inputs
 Design
When the 8K × 8 EPROM is used,
Address connections A12–A0 of the 8086 are connected to address
inputs A12–A0 of the EPROM.
The remaining nine address pins (A19–A13) are connected to the inputs
of 3-8 line decoder
8K x 8 EPROM.

= 23 x 1K = 23 x 210 = 213 B

equired EPROM is 64KB hence 8KB eight is required

 Therefore address lines required is13 line i.e A12 to A0
 A19 toA13 are connected to 3-8 line decoder 74138

BC are input select lines which are connected to A13,A14,A15

1= Input G1 is connected directly to A16.

2B: When all three address inputs (A17 A18 A19) are high, the output
of this NAND gate goes low and enables input G2B of the
74LS138.
10–4 8086 (16-Bit) MEMORY
INTERFACE
8086 has data bus is 16 bits M/IO
pin is used.
 Separate Bank Write
Strobes
The effective way to handle bank selection
is a separate write strobe for each bank.

his requires only one decoder to select a

16-bit-wide memory, which saves money
Fig 10–29 depicts generation of separate
8086 write strobes.
Separate read strobes for each bank are
usually unnecessary because 8086 read
only the byte of data they need at any given
time from half of the data bus.
 Figure 10–29 The memory bank write
selection input signals: HWR (high bank
write) and LWR (low bank write).

Memory in a system using separate write strobes is

decoded as 16-bit-wide
Figure 10–29 depicts the generation of separate 8086
write strobes for the memory.
a 74LS32 OR gate combines A0 with WR’ for the low
bank selection signal ( LWR’). ,
BHE’ combines with WR’ for the high bank selection
signal ( HWR’).
 Two 4K x 8 EPROM= 23 x 210 = 213 = A12 to A0
A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

two 4K x 8 EPROM= 23 x 210 = 213

= A12 to A0

two 4K x 8 RAM= 23 x 210 = 213 = A12 to A0

A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

two 4K x 8 RAM= 23 x 210 = 213 = A12 to A0