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Vls I Testing

The document discusses the importance of VLSI testing to identify faults during the design, fabrication, and packaging processes of chips. It differentiates between verification and testing, outlines various levels and types of testing, and highlights the significance of both chip-level and system-level testing. Additionally, it covers fault types, testing methods, and the objectives of functional and diagnostic testing.

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4 views17 pages

Vls I Testing

The document discusses the importance of VLSI testing to identify faults during the design, fabrication, and packaging processes of chips. It differentiates between verification and testing, outlines various levels and types of testing, and highlights the significance of both chip-level and system-level testing. Additionally, it covers fault types, testing methods, and the objectives of functional and diagnostic testing.

Uploaded by

naveendhanasekaran632
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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VLSI

TESTING

Overview and Need for Testing

PRESENTED BY NANDHINI
What is testing for?

● Possibility of errors during the design


process.
● There can even be bugs in the translation
process(viz. the CAD tools used).
● Possibility of faults during fabrication /
packaging.
● Necessary to test each and every chip
before they can be used.
● Billions of transistors is present-day VLSI
chips.
Basic Objective

• We use testing to determine the presence of


faults in a given circuit / chip.
• Fallacy: Testing is used to guarantee that a
circuit / a chip is free of faults.
• No amount of testing can give this guarantee.
• Using testing, we can increase out confidence in
the correct working of the circuit / chip.
• We usually use verification along with
testing(distinctly different objectives.
Difference between
VERIFICATION & TESTING
Verification guarantees the Testing tries to guarantee the
correctness of the design. correctness of the
manufactured circuits / chips.

Performed once before the Has to be performed on every


actual manufacturing of the manufactured device.
circuits / chips.

Primarily responsible for the Primary responsible for the


quality of the design. quality of the device that go to
the market.

Uses formal methods, Two steps involved: (a)Test


simulation, etc. Generation, (b) Test
Application.
When to do testing?

Can be carried out at Rule of thumb:


various levels: 1. Detecting a fault early
1. At the chip-level, when chips reduces the cost of testing.
are manufactured. 2. Empirical Rule: It is 10 times
2. At the board-level, when chips more expensive to test a
are integrated on the boards. device as we move to the
3. At the system-level, when next higher level( chip
several boards are assembled board system).
together
What are the Sources of Fault?

 Because of errors during the fabrication process-


Missing contact window, parasitic transistors, etc.
 Because of defects in the material(s)- Cracks or
imperfections in the substrate, surface impurities, etc.
 Because of ageing- Dielectric breakdown, electron
migration, etc.
 Because of defects during packaging-Contact
degradation, disconnection, etc.
Types of Faults
Faults

Permanent Non-Permanent

Transient Intermittent
Permanent Faults change the functional
behavior of a chip in a time-independent
(permanent) way.
• Design errors, incorrect connections, etc.
• Easier to detect.
Non-Permanent Faults occur randomly and
at unpredictable times and for unpredictable time
durations.
• Difficult to detect.
• The fault may not show up during testing.
• On-line testing is a popular method.
Transient Faults are caused due to
environmental conditions.
• Charged particles, variations in pressure,
vibration, temperature, etc.
• Example: Bit changes in RAMs caused by a-
radiation (called soft errors; no permanent
damage).
Intermittent Faults are caused by non-
environmental conditions, and behave like
permanent faults during the duration of the
failure.
• Loose connections, critical timing, changes in
parameter values, etc.
• May require repeated testing for detection.
CHIP LEVEL TESTING
 Chip level testing in VLSI in simple terms is providing a
predefined set of inputs and matching the outputs against the
desired outputs.
 If the outputs are as per the level of expectation, only then
the testing is successful.
What are the different types of Chip level
testing in VLSI?
There are two ways methodically we can segregate the testing process:

 Off-chip testing: For this part of testing, external equipment or toolkit is provided to
the chip test equipment. One such piece of equipment would be ATE or Automated
Test Equipment.

 On-chip testing: For this procedure, on the chip or embedded resources are put
together to detect any flaw or defect in the circuit.
As per testing circuits, it can be divided into two categories furthermore:
1.Combinational Circuit 2. Sequential Circuit Testing
Testing Scan path test
Fault Model BIST
Path Sensitizing
Fault Models:
It is noted as the circuit is going to be functionally faulty and incorrect if
there is any element wrong in the circuit. There can be multiple
categorizations of the fault model:
 Struck at Faults: When the circuit node gets the logic value fixed
permanently.

 Transistor Struck-open faults: In case the transistors are always at the


non-conducting level and it seems to be stuck there.

 Transistor Struck-on faults: When transistors are always in the conducting


stage and thus producing incorrect outputs.

 Delay Faults: Single propagation delay can cause serious deviation from
the desired output.

 Bridging Faults: When one or more nodes accidentally touch, it might


produce short-circuit which is known as Bridging faults.
PATH
SENSITIZATION
AIM:
To generate the test vectors that activates the fault and to
propagate its effect throughout the circuit.

STEPS:
1.Fault excitation
2.Fault propagation
3.Back tracking
Sequential Circuit Testing

Scan Path Technique: Non- Scanned Sequential


Circuit.
Sequential Circuit Testing
Scan Path Technique: Scanned Sequential Circuit
System Level Testing:
System level testing in VLSI involves testing the
complete system or System-on-Chip (SoC), where multiple
chips and components are integrated into one functioning unit.

Importance of System-Level Testing:

 Functional Validation: Ensures all IPs (Intellectual Properties) work


together as intended.
 Performance Verification: Checks speed, latency, and throughput.
 Power & Thermal Analysis: Verifies power consumption and heat
dissipation.
 Reliability & Stress Testing: Identifies failures under extreme conditions.
 Compatibility Testing: Ensures interoperability with software (OS, drivers,
applications).
1. Functional Testing:
Functional testing validates that the chip behaves
according to its specifications under real-world operating
conditions.
Types of Functional Testing:
 Boot Testing
 CPU & Multicore Testing
 Memory Subsystem Testing
 Peripheral & Interface Testingk
 Power Management Testing
2. Diagnostic Testing:
It helps to identify, isolate, and debug faults in the
system.
Types of Diagnostic Testing:
 Structural Diagnostics
 Logic Diagnostics

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