Lecture 1:

VHDL - Introduction

DIGITAL SYSTEM DESIGN THRO’

VHDL

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Introduction
 Hardware description languages (HDL)
 Language to describe hardware
 Two popular languages
 VHDL: Very High Speed Integrated Circuits
Hardware Description Language
 Developed by DOD from 1983
 IEEE Standard 1076-1987/1993/200x
 Based on the ADA language
 Verilog
 IEEE Standard 1364-1995/2001/2005
 Based on the C language

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Applications of HDL
 Model and document digital systems
 Different levels of abstraction
 Behavioral, structural, etc.
 Verify design
 Synthesize circuits
 Convert from higher abstraction levels to
lower abstraction levels

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Input-Output specification of circuit
 Example: my_ckt
 Inputs: A, B, C
 Outputs: X, Y
A  VHDL description:
X
B my_ckt entity my_ckt is
Y port (
S A: in bit;
B: in bit;
S: in bit;
X: out bit;

Y: out bit);
06/26/25 end my_ckt ; 4
 VHDL entity
 entity my_ckt is Datatypes:
 Name of the circuit
 In-built
port (  User-defined
 User-defined
A: in bit;  Filename same as circuit
B: in bit; A  name recommended
Example.
Example: X
S: in bit; B  Circuit name: my_ckt
my_ckt
X: out bit;  Filename: my_ckt.vhd
Y
Y: out bit S
); Direction of port
3 main types:
end my_ckt;  in: Input
Port names Note theabsence
out: Output
of semicolon
or  end
“;” at the inout: Bidirectional
of the last signal
Signal names and the presence at the end of
the closing bracket
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Built-in Datatypes
 Scalar (single valued) signal types:
 bit
 boolean
 integer
 Examples:
 A: in bit;
 G: out boolean;
 K: out integer range -2**4 to 2**4-1;
 Aggregate (collection) signal types:
 bit_vector: array of bits representing binary numbers
 signed: array of bits representing signed binary numbers
 Examples:
 D: in bit_vector(0 to 7);
 E: in bit_vector(7 downto 0);
 M: in signed (4 downto 0);
--signed 5 bit_vector binary number

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User-defined datatype
 Construct datatypes arbitrarily or using
built-in datatypes
 Examples:
 type temperature is (high, medium, low);
 type byte is array(0 to 7) of bit;

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Functional specification
 Example:
 Behavior for output X:
A
 When S = 0
X
X <= A B my_ckt
 When S = 1 Y
X <= B S
 Behavior for output Y:
 When X = 0 and S =0
Y <= ‘1’
 Else
Y <= ‘0’

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VHDL Architecture
 VHDL description (sequential behavior):
architecture arch_name of my_ckt is
begin
p1: process (A,B,S)
 begin
if (S=‘0’) then
X <= A;
else
X <= B;
end if;
Error: Signals defined as
if ((X = ‘0’) and (S = ‘0’)) then output ports can only be
Y <= ‘1’; driven and not read
else
Y <= ‘0’;
end if;

end process p1;

end;
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VHDL Architecture
architecture behav_seq of my_ckt is

signal Xtmp: bit;

Signals can only be
defined in this
begin place before the
p1: process (A,B,S,Xtmp)
begin begin keyword
if (S=‘0’) then
Xtmp <= A;
else
Xtmp <= B; General rule: Include all signals in
end if; the sensitivity list of the process
which either appear in relational
comparisons or on the right side of
if ((Xtmp = ‘0’) and (S = ‘0’)) then
Y <= ‘1’; the assignment operator inside the
else process construct.
Y <= ‘0’; In our example:
end if; Xtmp and S occur in relational
comparisons
X <= Xtmp; A, B and Xtmp occur on the right side of
end process p1; the assignment operators
end;
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VHDL Architecture
 VHDL description (concurrent behavior):

architecture behav_conc of my_ckt is

signal Xtmp: bit;

begin

Xtmp <= A when (S=‘0’) else

B;
Y <= ‘1’ when ((Xtmp = ‘0’) and (S = ‘0’)) else
‘0’;

X <= Xtmp;

end ;

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Signals vs Variables
 Signals
 Signals follow the notion of ‘event scheduling’
 An event is characterized by a (time,value) pair
 Signal assignment example:
X <= Xtmp; means
Schedule the assignment of the value of signal
Xtmp to signal X at (Current time + delta)
where delta: infinitesimal time unit used by
simulator for processing the signals

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Signals vs Variables
 Variables
 Variables do not have notion of ‘events’
 Variables can be defined and used only inside the
process block and some other special blocks.
 Variable declaration and assignment example:
process (…) Variables can only
variable K : bit; be defined and used
begin inside the process
… construct and can
be defined
-- Assign the value of signal only in
L to var. K
immediately this place
K := L;
…
end process;

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Simulation

 Simulation is modeling the output

response of a circuit to given input
stimuli
A
 For our example circuit: X
 Given the values of A, B and S B my_ckt
 Determine the values of X and Y
Y
 Many types of simulators used S
 Event driven simulator is used
popularly
 Simulation tool we shall use:
ModelSim

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Simulation
architecture behav_seq of my_ckt is
Time A B S Xtm Y XtmpVa X
signal Xtmp: bit;
‘T’ p r
begin
p1: process (A,B,S,Xtmp) 0- U U U ‘X’ ‘X ‘X’ ‘X
variable XtmpVar: bit; ’ ’
begin
0 0 1 0 ‘X’ ‘X ‘X’ ‘X
if (S=‘0’) then ’ ’
Xtmp <= A;
else 0+d 0 1 0 0 0 0 ‘X
Xtmp <= B; ’
end if;
0+2 0 1 0 0 1 0 0
if ((Xtmp = ‘0’) and (S = ‘0’)) then d
Y <= ‘1’;
else 1 0 1 1 0 1 0 0
Y <= ‘0’;
end if; Scheduled
Scheduled events
events
1+d 0 1 Scheduled
Assignments
1 1 0events
executed:
0 0
executed:
list: list:
XtmpVar = ‘X’
X <= Xtmp; 1+2 0 1 1 1 0 0 1
XtmpVar := Xtmp;
Xtmp = 0
Xtmp = (0,0+d)
d Xtmp = (0,0+2d)
(empty)
end process p1; Y =Y10= (0,0+d) Y = (1,0+2d)
end;
X =X0‘X’
= (‘X’,0+d) X = (‘0’,0+2d)

Assignments executed:
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XtmpVar = 0
Synthesis
 Synthesis:
Conversion of behavioral level description
to structural level netlist
 Abstract behavioral description maps to concrete
logic-level implementation
 For ex. Integers at behavioral level mapped to
bits at structural level
 Structural level netlist
 Implementation of behavioral description
 Describes interconnection of gates
 Synthesis tool we shall use:
Leonardo Spectrum

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Structural level netlist
 Behavior of our example
A
circuit: X
 Behavior for output X: B my_ckt
 When S = 0 Y
X <= A S
 When S = 1
X <= B
 Behavior for output Y:  Logic functions
 When X = 0 and S =0  Sbar = ~ S
Y <= 1  Xbar = ~ X
 Else  X = A*(Sbar) + B*S
Y <= 0  Y = (Xbar)*(Sbar)

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Structural level netlist
architecture behav_conc of my_ckt is
-- component declarations
 Gate level VHDL
signal Sbar, Xbar, W1, W2: bit; descriptions
(and, or, etc) are
begin described separately
G1: not port map(Sbar,S);
 Design in which other
G2: and port map(W1,A,Sbar);
design descriptions are
G3: and port map(W2,B,S);
included is called a
G4: or port map(X,W1,W2);
“hierarchical design”
G5: not port map(Xbar,X);
 A VHDL design is
G6: and port map(Y,Xbar,Sbar);
included in current
design using port map
end ; statement
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Other VHDL resources
 VHDL mini-reference by Prof. Nelson
 http://www.eng.auburn.edu/department/
ee/mgc/vhdl.html
 VHDL Tutorial: Learn by Example
by Weijun Zhang
 http://esd.cs.ucr.edu/labs/tutorial/

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