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2023 Topic 3 - Logic Minimization

The document covers the topic of Logic Minimization in Digital Electronics, focusing on the identification and simplification of Sum-of-Product (SOP) and Product-of-Sum (POS) expressions. It includes methods for using Karnaugh Maps for simplification and emphasizes the importance of standard forms in constructing truth tables. Key learning outcomes include recognizing minterm and maxterm notations and utilizing don't care conditions for logic function simplification.

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0% found this document useful (0 votes)
4 views56 pages

2023 Topic 3 - Logic Minimization

The document covers the topic of Logic Minimization in Digital Electronics, focusing on the identification and simplification of Sum-of-Product (SOP) and Product-of-Sum (POS) expressions. It includes methods for using Karnaugh Maps for simplification and emphasizes the importance of standard forms in constructing truth tables. Key learning outcomes include recognizing minterm and maxterm notations and utilizing don't care conditions for logic function simplification.

Uploaded by

karunginkongoki
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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EE008-3-2-DE Digital Electronics

Topic 3 : Logic Minimization

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 1


TOPIC LEARNING OUTCOMES

At the end of this topic, you should be able to:


1. Identify SOP and POS expressions, minterm and maxterm notations
2. Identify Standard SOP and POS expressions
3. Simplify the expression using Karnaugh Map
4. Utilize Don’t care conditions to simplify the logic function

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 2


Contents & Structure

• POS and SOP


• Minterm and Maxterm
• Karnaugh Map simplification

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 3


Recap From Last Lesson
• Boolean Algebra laws
• Boolean Algebra simplification

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 4


Teaching Contents

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 5


Standard Form of Boolean Expression

• All Boolean expression can be converted into two standard form:


– The sum‐of‐product form (SOP)
– The product‐of‐sum form (POS)
• These standardization makes evaluation, simplification and
implementation of Boolean expression more systematic and easier

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 6


Slide 6
Sum-of-Product

• SOP is defined as two or more product terms are summed by Boolean


addition expression. Example :
 AB +ABC Sum of product
Product term/ minterm
 A B  ABC  AC
• Domain of SOP expression: is the set of variables contain in the
expression either in complemented and uncomplemented form
• Example: the domain of expression AB  = A, B, C
ABC
• Example: the domain of expressionABC  CDE  B =CA,D B, C, D and E
• In SOP, a single overbar cannot extend more than one variable,
example : not SOP because
A B  ABC ABC
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 7
Slide 7
Sum-of-Product - AND / OR implementation of SOP expression

• Implementing an SOP expression simply requires ORing the


outputs of AND gates.
• A product term (minterm) is produced by AND operation.
• The Sum of product terms is produced by OR operation.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 8


Slide 8
Sum‐of‐Product (SOP): Standard SOP Form

• A standard SOP form must contain all of the variables in the


domain of the expression for each product term, example:
A B C  ABC  ABC
• Standard SOP forms are essential in constructing the truth table.
• In the following SOP form,

– How many minterms are there?


=> 3
– Is it a standard SOP form?
=> No
– How do we convert a Boolean expression into standard SOP form?

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 9


Slide 9
Sum‐of‐Product (SOP): Standard SOP Form

• To convert SOP to its standard form, we use Boolean expression:


A A
A( B  C )  AB  AC
• Example: Convert the following Boolean expression into SOP
standard form A BC  A B  ABC D
• Solution
– The domain of this SOP is: A, B, C and D. Take one term at a time,
– The first term, A BC missing D or D’. So multiply D  D 1as
follows;
A BC  A BC ( D  D )  A BCD  A BC D
– The second term, A B missing C or C’ and D or D’. So multiply
C  C 1 Dand
 D 1 as follows;
A B  A B (C  C )( D  D )
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 10
Slide 10
Sum‐of‐Product (SOP): Standard SOP Form

– The second term, A B missing C or C’ and D or D’. So multiply


C  C 1 Dand
 D 1 as follows;
A B  A B (C  C )( D  D )
A B  A BC  A BC ( D  D )
A B ( A BC  A BC )( D  D )
A B  A BCD  A BC D  A BC D  A BC D
– The third term, ABC D already in standard from (nothing missing).
Thus, the standard SOP form;

A BCD  A BC D  A BCD  A BC D  A BC D  A BC D  ABC D

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 11


Slide 11
Product-of-Sum

• POS is defined as two or more sum terms are multiplied. Example :


 (A+B)(A+B+C) Product of sum
Sum term/ maxterm
 (A  B )(A  B  C) (A  C)
• In POS, a single over bar cannot extend more than one variable,
example: (A  B )(A  B  C) Not POS because B  C

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 12


Slide 12
Product-of-Sum : AND / OR implementation of POS expression

• Implementing an POS expression simply requires ANDing the


outputs of OR gates.
• A sum term (maxterm) is produced by OR operation.
• The product of sum terms is produced by AND operation.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 13


Slide 13
Product-of-Sum (POS): Standard POS Form

• A standard POS form must contains all of the variables in the


domain of the expression for each sum term, example:
(A  B  C )( A  B  C) (A  B  C)
• Standard POS forms are essential in constructing the truth table.
• In the following POS form,

– How many maxterms are there?


=> 3
– Is it a standard POS form?
=> No
– How do we convert a Boolean expression into standard POS form?

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 14


Slide 14
Product-of-Sum (POS): Standard POS Form

• To convert POS to its standard form, we use Boolean expression:


A. A 0
A  BC ( A  B )( A  C )
• Example: Convert the following Boolean expression into POS standard form
• Solution ( A  B  C )( B  C  D )( A  B  C  D )
– The domain of this POS is: A, B, C and D. Take one term at a time,
– The first term, ( A  B  C )missing D or D’. So add D.D 0 as follows;
A  B  C  A  B  C  D.D ( A  B  C  D)( A  B  C  D)

– The second term,


( B  C  D ) missing A or A’. So add A. A 0
as follows;
B  C  D B  C  D  A. A ( B  C  D  A)( B  C  D  A)
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 15
Slide 15
Product-of-Sum (POS): Standard POS Form

– The second term, ( B  C  D ) missing A or A’. So add


A. A 0 as follows;

B  C  D B  C  D  A. A ( B  C  D  A)( B  C  D  A)
– The third term,( A  B  C  D ) is already in standard form ( nothing
missing).
– Thus the standard form;

( A  B  C  D)( A  B  C  D)( A  B  C  D)( A  B  C  D)

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 16


Slide 16
Exercises

• Convert the following Boolean expression into standard SOP form.

A( B  CD)
Convert the following Boolean expression into standard POS form.

( A  B )( B  C )

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 17


Slide 17
Standard SOP & POS expressions

• The importance in developing standard expressions:


– Constructing truth tables
– Karnaugh map simplification method

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 18


Slide 18
Truth Table - SOP to Truth Table
• Develop a truth table for the SOP expression :
• Domain = A, B, C : combinations = 23 = 8
• Determine the inputs that makes the product term/minterm = 1.
• A standard product term is equal to 1 for only one combination of variables values
• An SOP expression is equal to 1 only if one or more of the product terms in the
expression is equal to 1
• Currently , 3 product terms :
A BC 001
A BC 100
ABC 111
• Finally, fills up the truth table

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 19


Slide 19
Truth Table
SOP to Truth Table

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 20


Slide 20
Truth Table
POS to Truth Table
• Develop a truth table for the POS expression :
( A  B  C )( A  B  C )( A  B  C )
• Domain = A, B, C : combinations = 23 = 8
• Determine the inputs that makes the sum term/ maxterm = 0.
• A standard sum term is equal to 0 for only one combination of variables values
• An POS expression is equal to 0 only if one or more of the product terms in the
expression is equal to 0
• Currently , 3 product terms :
A  B  C 0  0  0
A  B  C 0  1  0
A  B  C 1  0  1
• Finally, fill up the truth table
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 21
Slide 21
Truth Table
POS to Truth Table
A B C F SUM
TERM/
MAXTERM
A B C
0 0 0 0
0 0 1 1
A B C
0 1 0 0
0 1 1 1
1 0 0 1
A B C
1 0 1 0
1 1 0 1
1 1 1 1

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 22


Slide 22
Boolean expression and Truth Table
• STEP 1: Convert expression to Standard SOP/POS.
• STEP 2: Determine domain and combinations of binary values at
input.
• STEP 3: Find the inputs values that make the term;
– Equal to 1 for SOP, e.g. ABC = 111.
– Equal to 0 for POS, e.g. A+B+C = 000.
• STEP 4: Fill the truth table (the remaining blanks with inverse
values).

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 23


Slide 23
Truth Table
• Make a truth table for the following functions:

a ) F  AB  AC
b) F ( A  C )( B  C )

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 24


Slide 24
Truth Table:
Truth Table to SOP Form
• Can write standard SOP expression simply from truth table.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 25


Slide 25
Truth Table:
Truth Table to POS Form
• Can write standard POS expression simply from truth table.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 26


Slide 26
Truth Table: Minterm and Maxterm Notation
• Each line in a truth table represents both a Minterm and Maxterm

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 27


Slide 27
Truth Table: Minterm and Maxterm Notation
• A Boolean function can be written in terms of Minterm or Maxterm
notation as shorthand method of specifying the function.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 28


Slide 28
Truth Table: Minterm and Maxterm to Truth Table
• Minterms correspond to ‘1’ of F, Maxterms correspond to ‘0’ of F in
truth table.
• Given minterm and maxterm forms as follow. Find the truth table.

Minterm Notation
F(A,B,C) =  m(1,2,6)
=
m  m m
1 2 6

Maxterm Notation
F(A,B,C) =  M (0,3,4,5,7)
= 0  M3  M4  M5  M7
M
= ( A  B  C )( A  B  C )( A  B  C )( A  B  C )( A  B  C )
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 29
Slide 29
KARNAUGH MAP (K-MAP)

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 30


Slide 30
K-map
• K‐map is represents by an array of cells in which each cell represents
a binary value of the input valuable.
• Karnaugh Mapping is used to minimize the number of logic gates
that are required in a digital circuit.
• This will replace Boolean reduction when the circuit is large.
• It provides a systematic method for simplifying Boolean expressions
and could produce the simplest SOP or POS expression possible.
• K‐map can be used for expressions with two, three, four and five
variables.
• Number of cells = 2n.
• For three variables (A,B,C) the number of cells = 23 = 8.
• For four variables (A,B,C,D) the number of cells = 24 = 16.
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 31
Slide 31
K-map
(2-variables)
• An array of four cells

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 32


Slide 32
K-map
(3-variable)
• An array of eight cells.
Gray Code

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 33


Slide 33
K-map
(4-variable)
• An array of sixteen cells. Gray Code

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 34


Slide 34
K‐Map:
Example
• Given the following standard SOP form, complete
the truth tableF and K‐map.
 A BC  ABC  ABC  ABC

• Truth Table F(A,B,C)


A B C F
0 0 0 0
0 0 1 1 A BC
0 1 0 1 ABC
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1 ABC
1 1 1 1 ABC
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 35
Slide 35
K‐Map:
Example
• Given the following SOP form, complete the truth table
and K‐map.

• Step 1:

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 36


Slide 36
K‐Map:
Example (Cont’d)
• Step 2:
– Transfer the standard SOP form, into the truth table and
complete K‐map.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 37


Slide 37
K-map Simplification
(Grouping)
• After SOP expression has been mapped, minimum expression is
obtained by grouping the 1s and determining the minimum
SOP expression from the K‐map.
• When grouping the 1s, the goal is:
– to maximize the size of the groups
– to minimize the number of groups

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 38


Slide 38
K-map Simplification
(Grouping) (cont’d)
• Rules for grouping of 1s:
– A group must contain either 1, 2, 4, 8, or 16 cells. For x‐variable
K‐map, 2x cells is maximum.
– Each cell in a group must be adjacent to one or more cells in
that same group, but all cells in the group don’t have to be
adjacent to each other.
– Always include the largest possible number of 1s in a group
– Each 1 on the map must be included in at least one group. The
1s already in a group can be included in another group as long
as the overlapping groups include common 1s.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 39


Slide 39
K-map Simplification
(Grouping) (cont’d)

• Example: Group the 1s in each of the K‐map.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 40


Slide 40
K-map Simplification
(Grouping) (cont’d)
• Solution:

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 41


Slide 41
Determine the minimum SOP
from K‐map
• The following rules are applied to find the minimum product terms and the
minimum SOP expression:
– STEP 1: Group the cells that have 1s.
– STEP 2: Determine the minimum product term for each group.

• For a 3‐variable K‐map:


– A 1‐cell group yields a 3‐variable product term.
– A 2‐cell group yields a 2‐variable product term.
– A 4‐cell group yields a 1‐variable product term.
– An 8‐cell group yields a value of 1 for the expression.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 42


Slide 42
Determine the minimum SOP from K‐map
• For a 4‐variable K‐map:
– A 1‐cell group yields a 4‐variable product term.
– A 2‐cell group yields a 3‐variable product term.
– A 4‐cell group yields a 2‐variable product term.
– An 8‐cell group yields a 1‐variable product term.
– An 16‐cell group yields a value of 1 for the expression

– STEP 3: When all the minimum product term are derived from
K‐map, they are summed to form SOP expression.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 43


Slide 43
Determine the minimum SOP from
K‐map

A BC

BC 00 01 11 10
A
0 0 1 0 1
1 0 0 1 1 BC

AB

Expression is minimized when taking large cell possible


F  A BC  AB  BC

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 44


Slide 44
Determine the minimum SOP
from K‐map
• Group the 1s and find the minimum SOP expression in
the K‐Map below:
BC 00 01 11 10
A
0 1 1 0 1
1 1 0 1 1

00 01 11 10
CD
AB
00 1 1 0 0
01 1 1 1 1
11 0 0 0 0
10 0 1 1 0

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 45


Slide 45
Determine the minimum SOP
from K‐map

00 01 11 10
CD
AB
00 1 0 0 1
01 1 1 0 1
11 1 1 0 1
10 1 0 1 1

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 46


Slide 46
Determine the minimum POS
from K‐map
• K‐map can also be used to obtain POS expression by grouping 0s.
• Example: Group the 0s and find the minimum POS expression in the
K‐Map below:
00 01 11 10
BC
A
0 0 1 0 1
1 0 0 1 1

00 01 11 10
CD
AB
00 1 1 0 0
01 1 1 1 1
11 0 0 0 0
10 0 1 1 0
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 47
Slide 47
K‐Map:
Don’t Care Condition

• Don’t care is the condition when the output can either be ‘1’ or ‘0,’
which is denoted by ‘X’ in the truth table or K‐Map.
• For both SOP and POS minimum expression, ‘X’ can be included or
ignored.
• Example: Find the minimum SOP expression in the K‐Map below:

00 01 11 10
CD
AB
00 0 1 1 0
01 0 1 1 X F  AD  AB
11 1 1 X 1
• If the X is replaced
10 by 0, find
0 0 minimum
the 0 0 expression.
SOP
F  AD  ABC  AB D
EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 48
Slide 48
K‐Map:
Don’t Care Condition
• Example: Find the minimum POS expression in the K‐Map below:

00 01 11 10
CD
AB
00 1 0 0 1
01 0 0 1 1
11 X X 1 1
10 1 0 X 1
F ( B  C )( B  D)

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 49


Slide 49
COMBINATIONAL LOGIC DESIGN

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 50


Slide 50
Combinational Logic Design
• The design steps:
1. Identify the number of inputs and outputs of
the system,
(i.e. obtain the block diagram)
2. Derive the truth table for the system.
3. Using K‐Map, obtain the minimum expression.
4. Implement the circuit using logic gates.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 51


Slide 51
Combinational Logic Design:
Example
Example(1):
A combinational circuit has 3 inputs A, B, C and output F. F is true for
following input combinations
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
(i) Write the Truth table for F. Use the convention True=1 and False
= 0.
(ii) Write the simplified expression for F in SOP form.
(iii) Write the simplified expression for F in POS form.
(iv) Draw logic circuit using minimum number of 2-input NAND gates.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 52


Slide 52
Combinational Logic Design:
Example

A combinational logic circuit has one output Z and 4-bit


inputs (A, B, C, D) representing the binary numbers. The
output, Z should be HIGH (‘1’) if the input is at least 3 but
not greater than 10
• Obtain the truth table of this circuit
• Derive the simplified Boolean expressions from the
above truth table using Karnaugh map.
• Realize the above Boolean expressions using logic
gates.

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 53


Slide 53
Review Questions

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 54


Summary / Recap of Main Points

• What was covered:-


– Standard SOP and POS
– Simplify the expression using Karnaugh Map
– Simplify the truth table using Karnaugh Map
– Utilise “Don’t care condition to simplify the logic function

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 55


What To Expect Next Week

In Class Preparation for Class


• Kmap minimization exercises • Combinational logic circuit
• Combinational logic circuit design design
steps

EE008-3-2-DE Digital Electronics Logic Minimization SLIDE 56

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