Peripheral Interfacing and 8237 DMA

controller
 Input-Output Interfacing
Peripheral Interfacing:
I/O programming: Programmed I/O, Interrupt Driven
I/O, DMA I/O interface: serial and parallel
communication, memory I/O mapped I/Os.
Peripheral Devices: 8237 DMA controller, 8255-
Programmable peripheral interface, 8253/8254
Programmable timer/counter.8259 programmable
Interrupt Controller.
 Peripheral Interfacing

Introduction - Any application of a microprocessor based

system requires the transfer of data between external circuitry to
the microprocessor and microprocessor to the external
circuitry .User can give information to the microprocessor based
system using keyboard and user can see the result or output
information -from the microprocessor based system with the help
of display device. The transfer of data between keyboard and
microprocessor, and microprocessor and display device is called
input/ output data transfer
Input/Output I/O instructions vary drastically from
architecture to architecture. The scheme for handling I/O
usually fits into one of the following patterns:
•Programmed I/O with busy waiting
•Interrupt-driven I/O
•DMA I/O
 Input Output Techniques
• Programmed I/O
– CPU issues I/O command then “polls” device until I/O complete
– then (e.g. read) CPU transfers new item obtained from device
• Interrupt driven I/O
– CPU issues I/O command then device “interrupts” CPU when
complete
– then (e.g. read) CPU transfers new item obtained from device
• Direct Memory Access (DMA) I/O
– CPU asks DMA to perform transfer between I/O and memory
– DMA issues I/O command then (e.g. read) when I/O complete,
DMA transfers new item into memory
Programmed I/O
• CPU has direct control over I/O
• Sensing status
• Read/write commands
• Transferring data
• CPU waits for I/O module to complete operation
• Wastes CPU time (“busy waiting”)
 Programmed I/O
CPU executing Typical Polled Operation
software
instructions

CPU issues I/O command

device performs
CPU reads device status bits operation

no
status = done/ready?
CPU is
yes
“busy waiting”
in polling loop
Interrupt Driven I/O
Basic Operation

1. CPU issues read command

2. I/O module gets data from peripheral while CPU does
other work
3. I/O module interrupts CPU
4. CPU requests data
5. I/O module transfers data
Advantage: Overcomes CPU busy waiting loops
• No repeated CPU checking of device
 Interrupt Driven I/O
CPU Viewpoint

1. Issue Read command done by CPU hardware

NOT software instructions!
2. Do other work
3. Check for interrupt at end of each instruction cycle
4. If interrupted:
a) Save context (registers)
b) Process interrupt
• Fetch data & store execute ISR
c) restore saved context and resume (software)
 Interrupt Driven I/O and
DMA I/O provides an alternative to eliminate busy waiting.
Interrupt-driven
The I/O device will send an interrupt when it has data for the CPU.
Often this is accomplished by setting an Interrupt Enable bit in a
device register.

• Interrupt-driven I/O usually requires an interrupt every time a

character is read/written and processing an interrupt can be
expensive.

• CPU starts I/O device. Let it generate an interrupt when the job is
done.
• Disadvantages: Too many interrupts generated.
• DMA usually has separate chip do the I/O transfer for the CPU.
When the job is done one interrupt is generated.
Direct Memory Accessing; the 8237 DMA Chip
 DMA
Direct Memory Access (DMA) is a method of allowing data to be moved
from one location to another in a computer without intervention from the
central processor (CPU). It is also a fast way of transferring data within
(and sometimes between) computers.

What is the advantage of using DMA?

Transfer of data is faster

What does the DMA need to know to transfer a block of data?

When the DMA needs to transfer a block of data from memory to an I/O device such as a disk, it
must know:
a) the address of the beginning of the block (address of first byte of data), and
b) the number of bytes (count) it needs to transfer.
 Direct Memory Access (DMA)
There is often a need to transfer a large number of
data between memory and peripherals such of data
between memory and peripherals such as disk
drives.
Using the CPU to transfer such data is too slow.
DMA is a mechanism to bypass the CPU and provide
direct connection between peripherals and
memory. Thus DMA method is more efficient than
normal data transfer . During the transfer process,
DMA will take control of the system busses and
transfer take control of the system busses and
transfer data between RAM and peripheral devices.
Since there is only one set of busses (data bus, address bus, and
control bus), how do the DMA and CPU share the buses to transfer
data?
When the system is turned on, the switches are in the A position, so the
buses are connected from the microprocessor to the system memory and
peripherals. Microprocessor then executes the program until it needs to
read a block of data from the disk. To read a block of data from the disk
microprocessor sends a series of commands to the disk controller device
telling it to search and read the desired block of data from the disk. when
disk controller is ready to transfer first byte of data from disk, it sends
DMA Jest DRQ signal to the DMA controller. Then DMA controller
sends a hold request Q signal to the microprocessor HOLD input. The
microprocessor responds this HOLD lal by floating its buses and sending
out a hold acknowledge signal HLDA, to the ll\ controller. When the
DMA controller receives the HLDA signal, it sends a control lal to
change switch position from A to B. This disconnects the microprocessor
from the es and connects DMA controller to the buses.
 Address Latches
AD0- AD15 A Address Bus

ALE
B
Data Bus
A
Data Bus
Micro
Memory
Processor B

Control Bus A
Control Bus
OR , IOW
HLDA HOLD MEMR , MEMW B

HRQ
DMA
HLDA Controller Control Bus Peripheral
Device
HREQ (Disk
OR, IOW Controller)
MEMR , MEMW
DACK0
 DMA Protocol (I)
 DMA operation is initiated by DMA operation is initiated by
 Hardware, peripheral I/O sends a request to DMA controller (DMAC)
by pulling DREQ (DMA request) high (DMAC)
Software, CPU write a request command to DMA/C.
The DMAC will put a high on its HRQ (Hold request), signaling the
CPU through its HOLD pin that it needs to use the buses.
 The CPU will finish the present bus cycle and respond to the DMA
request by putting high on its HDLA (hold the DMA request by putting
high on its HDLA (hold ack .).HOLD must remain active high as long
as DMA is performing its task.
DMAC will activate DACK (DMA DMAC will activate DACK (DMA ack )
which tells the peripheral device that it will start to transfer the data.

After the DMAC has finished its job it will deactivate

HRQ, signaling the CPU that it deactivate HRQ, signaling
the CPU that it can regain control over its buses.
 Features of 8237 A
1. It has 4 identical channel allow external devices are directly transfer
information to/from the system memory.
2. It also allows memory-to-memory data transfer.
3. The 8237 A is designed to be used in conjunction with an external 8-
bit address register such as the 8282. It contains four independent
channels and can be expanded to any number of channels by cascading
additional controller chips.
4. Each channel has a full 64K address and word count capability .
5. DMA controllers 8237 A, 8237 A-4, 8237 A-5 operate with 3 MHz, 4
MHz, and 5 MHz, respectively. The DMA controller 8237A-5 can
transfer up to 1.6 Mbytes/second.
Control Logic: The 8237 A contains three basic blocks of control logic.
a) Timing Control Block: It generates internal timing and external control signals for ! the
8237A.
b) Program Command Control Block: It decodes various commands given to the 8237 A by the
microprocessor before servicing a DMA request. It also decodes the Mode Control Word, which
is used to select the type of DMA during the servicing.
c) Priority Encoder Block: It resolves the priority between DMA channels requesting service
simultaneously.
Internal Registers: The 8237 A contains 344 bits internal memory in the form of registers. Table
gives the name, size and number of each register. The detailed description and bit pattern of each
register is given in the next section.
•8237 supports four DMA channels
•It has the following internal registers
* Current address register
» One 16-bit register for each channel
» Holds address for the current DMA transfer
* Current word register
» Keeps the byte count
» Generates terminal count (TC) signal when the count goes from zero to
FFFFH
* Command register
» Used to program 8257 (type of priority, …)
 Mode register Each channel can be programmed to
» Read or write
» Autoincrement or autodecrement the address
» Autoinitialize the channel
* Request register
» For software-initiated DMA
* Mask register
» Used to disable a specific channel
* Status register
* Temporary register
» Used for memory-to-memory transfers
» 8237 supports four types of data transfer
– Single cycle transfer
 Only single transfer takes place
 Useful for slow devices
– Block transfer mode
 Transfers data until TC is generated or external EOP signal is
received
– Demand transfer mode
 Similar to the block transfer mode
 In addition to TC and EOP, transfer can be terminated by
deactivating DREQ signal
– Cascade mode
 Useful to expand the number channels beyond four
DMA Operation: DMA, 8237A can operate in two major cycles, idle cycle and active
cycle.
a) Idle cycle: When no channel is requesting service, the 8237 A enters the idle cycle.
In this cycle the 8237 A polls the DREQ lines every CLOCK cycle to determine if any
channel is requesting a DMA service. Microprocessor configures DMA channels in the
DMA idle cycle.
b) Active cycle: In this mode DMAC transfers data in one of the four modes.
Single Transfer Mode
Block Transfer Mode
Demand Transfer Mode
Cascade Mode

Single Transfer Mode In this mode device can make only one transfer (byte or word). After each
transfer DMAC gives the control of all buses to the microprocessor. Due to this microprocessor
can have access to the buses on a regular basis.
It allows the DMAC to time share the buses with the microprocessor, hence this mode is most
commonly used.
The operation of the DMA in a single transfer mode is as given below :
1. I/O device asserts DRQ line when it is ready to transfer data. .
2. The DMAC asserts HLDA line to request use of the buses from the microprocessor.
3. The microprocessor asserts HLDA, granting the control of buses to the DMAC.
4. The DMAC asserts DACK to the requesting I/O device and executes DMA bus cycle, resulting
data transfer .
5. I/O device deasserts its DRQ after data transfer of one byte or word.
6. DMA deasserts DACK line.
7. The word/byte transfer count is decremented and the memory address is incremented.
8. The HOLD line is deasserted to give control of all buses back to the microprocessor .
9. HOLD signal is reasserted to request the use of buses when I/O device is ready to transfer
another byte or word. The same process is then repeated until the last transfer.
10. When the transfer count is exhausted, TC is generated to indicate the end of the
transfer.
Block I Burst Transfer Mode
In this mode device can make number of transfers as programmed in the word count register.
After each transfer word count is decremented by 1 and the address is decremented or
incremented by 1. The DMA transfer is continued until the word count "rolls over" from zero to
FFFFH, a terminal count (TC) or an external END of Process (EOP) is encountered. Block
transfer mode is used when the DMAC needs to transfer a block of data.
The operation of DMA in block transfer mode is as given below:
1. I/O device asserts DRQ line when it is ready to transfer data.
2. The DMAC asserts HLDA line to request use of the buses from the microprocessor.
3. The microprocessor asserts HLDA, granting the control of buses to the DMAC
4. The DMAC asserts DACK to the requesting I/O device and executes DMA bus
cycle, resulting data transfer.
5. I/O device deasserts its DRQ after data transfer of one byte or word.
6. DMA deasserts DACK line.
7. The word/byte transfer count is decremented and the memory address is incremented.
8. When the transfer count is exhausted, the data transfer is not complete and DMAC wait for
another DMA request from the I/O device,indicated that it has another byte or word to
transfer.When DMAC receive DMA request step through are repeated.
9. Microprocessor then deasserts the HLDA signal to tell the DMAC that it has
resumed control of the buses.
Demand Transfer Mode In this mode the device is programmed to continue making
transfers until a TC or external EOP is encountered or until DREQ goes inactive.
The operation of DMA in demand transfer mode is as given below:
1. I/O device asserts DRQ line when it is ready to transfer data.
2. DMAC asserts HLDA line to request use of the buses from the microprocessor.
3. The microprocessor asserts HLDA, granting the control of buses to the DMAC.
4. The DMAC asserts DACK to the requesting I/O device and executes DMA bus
cycle, resulting data transfer. "
5. I/O device deasserts its DRQ after data transfer of one byte or word.
6. DMA deasserts DACK line.
7. The word/byte transfer count is decremented and the memory address is
incremented.
8. The DMAC continues to execute transfer cycles until the I/O device deasserts
DRQ indicating its inability to continue delivering data. The DMAC deasserts
HOLD signal, giving the buses back to microprocessor. It also deasserts DACK.
9. I/O device can re-initiate demand transfer by reasserting DRQ signal.
10. Transfer continues in this way until the transfer count has been exhausted.
 Cascade Mode

DMA channels can be expanded using this mode. Fig. shows that two addition devices
are cascaded to the master device using two channels of the master device. This two
level DMA system. In this the HRQ and HLDA signals from the additional 8237 A are
connected to the DREQ and DACK signals of a channel of the master 8237 A. This
allows the DMA requests of the additional devices to communicate through the priority
network circuitry of the preceding device. Note: More 8237As can be added by adding
more levels in the DMA system.
Fig shows the detail connections for master and slave DMAC's.
Transfer Types
Memory-to-Memory Transfer
In this mode block of data from one memory address is moved to another memory
address. In this mode current address register of channel 0 is used to point the source
address and the current address register of channel 1 is used to point the destination
address in the first transfer cycle, data byte from the source address is loaded in the
temporary register of the 8237 A and in the next transfer cycle the data from the
temporary register is stored in the memory pointed by destination address. After each
data transfer current address registers are decremented or incremented according to
current settings. The channel 1 current word count register is also decremented by 1
after each data transfer.
Autoinitialize
In this mode, during the initialization the base address and word count registers are
loaded simultaneously with the current address and word count registers by the
microprocessor.
After the first block transfer i.e. after the activation of the EOP signal, the original
values of the current address and current word count registers are automatically
restored from the base address and base word count register of that channel. After
autoinitialization the channel is ready to perform another DMA service, without CPU
intervention.
Priority
In the 8237 A there are two priority selection options. 1. Fixed. Priority . 2. Rotating Priority.
1 Fixed Priority
In the fixed priority channel 0 has the highest priority and the channel 3 has the lowest priority.
Table shows the priority ratings.
Priority Channel
Highest 1 0
2 1
3 2
Lowest 4 3
Rotating Priority
In this, channel being serviced gets the lowest priority and the channel next to it gets the highest
priority as shown in Fig.

With rotating priority in a single chip DMA system, any device requesting service is guaranteed to be
recognized after no more than three higher priority services have occurred. This prevents anyone channel
from monopolizing the system.
 Register Description
1. Current Address Register: Each channel has 16-bit current address
register. This register stores the value of the address used during DMA
transfers. The address in the current address register is automatically
incremented or decremented after each transfer. This register is loaded or
read by the microprocessor and it also be re-initialized back to its
original value after EOP in the autoinitialization mode.
2. Current Word Register: Each channel has a 16-bit current word count
register. This register determines the number of transfers to be
performed. After each transfer the contents of word count register is
decremented by 1.
3. Base Address and Base Word Count Registers: Each channel has
base address and base word count registers. These 16-bit registers store
the original value of their associated current registers. During
autoinitialization these values are used to restore the current registers to
their original values. The base registers are stored simultaneously with
their corresponding current registers.
Command register • It is an 8-bit register that controls the operation of the 8237.
• It must be programmed by the CPU.
• It is cleared by the RESET signal from the CPU or the master clear instruction of the
DMA.

• The 8237 is capable of

transferring data
1. from a peripheral device to
memory (reading from disk)
2. from memory to a peripheral
device (writing the file into disk)
3. from memory to memory
Mask Register - Each channel has associated with it a mask bit which can be set to disable an incoming DREQ . Each bit of
the 4-bit Mask register may also be set or cleared separately or simultaneously under software control. The entire register is also set
by a Reset or Master clear. This disables all hardware DMA requests until a Clear Mask Register instruction allows them to occur.
The instruction to separately set or clear the mask bits is similar in form to that used with the Request register. Refer to the following
diagram and Figure 4 for details. When reading the Mask register, bits 4-7 will always read as logical ones, and bits 0-3 will display
the mask bits of channels 0-3, respectively. The 4 bits of the Mask register may be cleared simultaneously by using the Clear Mask
Register command (see software commands section).
Mode Register - Each channel has a 6-bit Mode register associated with it.
When the register is being written to by the microprocessor in the Program
condition, bits 0 and 1 determine which channel Mode register is to be written.
Status Register - The Status register is available to be read out of the 82C37A by the microprocessor. It
contains
information about the status of the devices at this point. This information includes which channels have reached a
terminal count and which channels have pending DMA requests. Bits 0-3 are set every time a TC is reached by
that channel or an external EOP is applied. These bits are cleared upon RESET, Master Clear, and on each
Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service, regardless of the mask
bit state. If the mask bits are set, software can poll the Status register to determine which channels have DREQs,
and selectively clear a mask bit, thus allowing user defined service priority. Status bits 4-7 are updated while
the clock is high, and latched on the falling edge. Status Bits 4-7 are cleared upon RESET or Master Clear.
 Program Example
Write an initialization program to transfer of data from a peripheral to memory for the
following specifications
1)Bytes to be transferred = 256
2) Memory starting address = 2050H
3) Channel used. = 1
4) Priority-Rotating
5) Extended write disabled
6) DREQ senses active low
7) DACK senses active low
8) Mode of transfer: Block transfer
Register Address
Command 88H
Mode 8BH
Current word count 83H
for channel
Current Address 82H
for channel
Solution:
i) The number of bits to be transferred i.e. N=256 hence the terminal count is
N-1=255=FFH. The 16 bit TC value is 00FFH.The value must be loaded
into current word register
ii) The starting address of memory is 2050H, hence value must be loaded
into current address register.
Command Register
0 1 0 1 0 0 0 0 = 50H

Mode Register
1 0 1 1 0 0 0 1 = B5H

Source Program :
MOV AL, 50H ; Load Command word
OUT 88H, AL ; Send Command word
MOV AL, 50H ; Load lower byte of address
OUT 82H, AL ; Send lower byte of address
MOV AL, 20H ; load higher byte of address
OUT 82H, AL ; send higher byte of address
MOV AL, FFH ; Load lower byte of count
OUT 83H, AL ; Send lower byte of count
MOV AL, 00H ; load higher byte of count
OUT 83H, AL ; send higher byte of count
MOV AL, B5H ; Load mode word
OUT 8BH, B5H ; Send mode word