Dr.N.G.

P Institute of Technology
Coimbatore – 641
048
Unit - 1

Basic Structure of a Computer

System
Instructions and
Instruction
Sequencing
 Instructio
ns
• Number of operation and instruction are executed
based on the CPU which means that can be
represented as machine instruction.
• Machine instructions are in the form of binary codes.
• If particular task has been completed with the help of
binary code then it is known as machine language
program.
• It also holds elements of instruction.

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 Elements of
instruction
• Operation code: specifies the operation to be
performed, operations are represented in the form of
binary codes.
• Source and destination operand: specifies the operand
field of Source and Destination.
• Source operand address: operation specified by the
instruction may require one or more source operands.
• Destination operand: operation executed by the
CPU may produce the result, since results are stored
in destination operand.
• Next instruction address: Next executable
instruction after completion of current instruction

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Location for source and destination
operands
• Processor registers, main memory, I/o device
• Immediate value: value of source operand may be in the
instruction itself.
• Representation of instruction:
OPCODE OPERAND OPERAND
ADDRESS 2
ADDRESS1
• Opcode: 4 bits
• Opernad 1 and 2 : 6 bits

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 INSTRUCTION TYPES
1. According to operation: based on the instruction
operation instruction set can be differentiated.
• Data processing: arithmetic and logical instruction,
performs both arithmetic and logical operation.
• Data storage: memory instruction, performs the
operation using register.
• Instruction must be transferred from CPU register to
memory register.
• Data movement: data transfer instruction, holds the
transfer of data from CPU register and I/O devices

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“Must-Perform” Operations

• Data transfers between the memory and the processor

registers
• Arithmetic and logic operations on data
• Program sequencing and control
• I/O transfers
Register Transfer Notation

• Identify a location by a symbolic name standing for its

hardware binary address (LOC, R0,…)
• Contents of a location are denoted by placing square brackets
around the name of the location (R1←[LOC], R3 ←[R1]+[R2])
• Register Transfer Notation (RTN)
 REGISTER TRANSFER NOTATION

• Need to describe the transfer of information from one location to another.

For ex
memory locations LOC,PLACE, A,VAR2;
processor register R0, R5;
I/O register DATAIN, OUTSTATUS,
• The contents of a location are denoted by placing square brackets.
Thus, the expression
R1 ← [LOC]
means that the contents of memory location LOC are transferred into processor register R1.
ASSEMBLY LANGUAGE NOTATION

Another type of notation to represent machine

instructions and programs. For example,
An instruction that causes the transfer between
from memory location LOC to processor
register R1, is
specified by the statement
Move LOC,R1
The contents of LOC are unchanged by the
execution of this instruction, but the
oldcontents of register R1 are overwritten.
The second example of adding two numbers
contained in processor registers R1and R2 and
placing their sum in R3 can be specified by the
assembly language statement
Add R1,R2,R3
Assembly Language Notation

• Represent machine instructions and

programs.
• Move LOC, R1 = R1←[LOC]
• Add R1, R2, R3 = R3 ←[R1]+[R2]
• As another example,
• consider the operation that adds the contents of
registers R1and R2, and then places their sum into
register R3.
• This action is indicated as
• R3 ← [R1] + [R2]
• This type of notation is known as Register Transfer
Notation (RTN).
• Note that right-hand side -always denotes a value,
• left-hand side -isthe name of a location
• where the value is to be placed, overwriting the
old contents of the location.
BASIC INSTRUCTION TYPES

C = A + B-> C<-[A]+[B]
Addition of 2 numbers in high level language.
Three Address instruction format
Operation Source1,Source2,Destination
Can be represented as
Add A,B,C
A,B are source operands
C Destination operands,Add is the operation to
be performed on the operands.
32-bit address space, a 3-address instruction is
too large to fit in oneword for a
reasonableword length.

An alternative approach , two-address

instructions of the form
Operation
Source,Destination

An Add instruction of this type is

Add A,B
which performs the operation B←[A] + [B].
When the sum is calculated, the result is sent
to the memory and stored in location B,
replacing the original contents of thislocation.
This means that operand B is both a source
MOV B,C
Performs the operation C<-[B] (i.e) copy the
contents of B to C.
Even 2 address instr will not fit into one word for
usual address size.

Machine instructions specify only one

operand,when a 2nd operand is needed,
A processor register called accumulator used for
this purpose.
Thus, the one-address instruction
Add A < Add the contents of memory location A to
the contents of the accumulator register >

Load A < copies the contents of memory location

A into the accumulator>

Store A < copies the contents of the accumulator

into memory locationA.>
Using only one-address instructions, the operation
C←[A]+[B] can be performed.
• In processors where arithmetic operations are
allowed only on operands that are inprocessor
registers, the C = A + B task can be performed by
the instruction sequence

• Move A,Ri <copies the [mem.loc A] into reg Ri >

• Move B,R j < copies the [mem.loc B] into reg Rj>
• Add Ri,R j <add the contents of registers Ri &
Rj>
• Move R j,C <copies the contents of register Rj
into mem loc C>
 Instruction Formats

• Three-Address Instructions
• ADD R1, R2, R3 R1 ← R2 + R3
• Two-Address Instructions
• ADD R1, R2 R1 ← R1 + R2
• One-Address Instructions
• ADD M AC ← AC + M[AR]
• Zero-Address Instructions
• ADD TOS ← TOS + (TOS – 1)
• RISC Instructions
• Lots of registers. Memory is restricted to Load &
Store

Opco Operand(s) or
de Address(es)
Instruction Formats

Example: Evaluate (A+B)  (C+D)

• Three-Address
1. ADD R1, A, B ; R1 ← M[A]
+ M[B]
2. ADD R2, C, D ; R2 ← M[C]
+ M[D]
3. MUL X, R1, R2 ; M[X] ← R1 
R2
Instruction Formats

Example: Evaluate (A+B)  (C+D)

• Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 +
M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 +
M[D]
5. MUL R1, R2 ; R1 ← R1  R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats

Example: Evaluate (A+B)  (C+D)

• One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC +
M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC +
M[D]
6. MUL T ; AC ← AC 
M[T]
7. STORE X ; M[X] ← AC
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A +
B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C +
D)
7. MUL ; TOS ←
(C+D)(A+B)
8. POP X ; M[X] ← TOS
Instruction Formats
Example: Evaluate (A+B)  (C+D)
• RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 +
R2
6. ADD R3, R3, R4 ; R3 ← R3 +
R4
7. MUL R1, R1, R3 ; R1 ← R1 
R3
8. STORE X, R1 ; M[X] ← R1
Using Registers

• Registers are faster

• Shorter instructions
• The number of registers is smaller (e.g. 32 registers need 5
bits)
• Potential speedup
• Minimize the frequency with which data is moved back and forth
between the memory and processor registers.
 Instruction Execution and Straight-Line Sequencing

AddressContents Assumptions:
- One memory operand
i
Begin execution here Move
A,R0
i+ 4 AddB,R0 3-instruction
program per instruction
R0,C segment - 32-bit word length
i+ 8 Move
- Memory is byte
addressable
A - Full memory address
can be directly specified
B Data
the for in a single-word instruction
program
Two-phase
C procedure
-Instruction
fetch
-Instruction
Figure 2.8. A program for C ¬ [A] + [B].
The processor contains a register
program counter (PC) - holds the address of
the instruction to be executed next.

Begin program execution,

- The address of 1st instruction must be
placed into the PC.

- The processor control circuits use the

information in the PC to,
fetch and execute instructions, in the order of
increasing addresses. This is called straight-line
sequencing.
During the execution of each instruction,
PC incremented by 4 to point next instruction.

(i.e) i,i+4,i+8,i+12.

which is the address of the first instruction of

the next program segment.
 Execution of instruction takes place
in 2 phases

Instruction Fetch-:
• Instruction fetched from the memory
loc – address is in PC
• Place the instruction to the
IR(Instruction Register)
Instruction Execute:
• Fetching operands from mem or pcr
registers
• Performing arithmetic and logic
operations.
• Storing the result in destination
 i Move
NUM1,R0
Branching i+4 AddNUM2,R0
i+8 AddNUM3,R0

•
•
• n,R0
i+4n-4 AddNUM
i+4n Move
R0,SUM

•
•
SUM •
NUM1
NUM2

•
•
NUMn •

Figure 2.9. A straight-line program for adding n number

Task – adding a list of n numbers
Addresses of n numbers given as – NUM1,NUM2…
NUMn &
Separate add instruction used to add each number to
[R0].
Result- stored in mem loc SUM.
 Move N,R1
Clear R0
Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement
R1
Branch target Branch>0
LOOP
Move R0,SUM
Conditional branch
•
•
SUM •
N n
NUM1
igure 2.10. Using a loop to add n numbers.
NUM2

•
•
NUM n •
• Loop starts at location loop & ends at
instruction Branch>0
• During each pass ,address of next list entry
is determined and it is fetched & added to R0.
• Register R1- counter determines number of
times the loop to be executed.
• [N] – stored in R1.
• Decrement R1- reduces the [R1] by 1 each
time through the loop.
• Execution repeated- decrement operation >0
Branch Instruction
This insruction loads a new value into the PC.
Pcr fetches and executes the instruction at this
new address – branch target
Instead of fetches the instruction present,next to
branch instruction.
Conditional branches- only if a specified condtion
is satisfied.
If not PC incremented – fetches the next
instruction in sequential order.
Branch > 0 LOOP
Cond branch instruction causes a branch to LOOP
– if the result R1>0
Repeated till R1<0.
After nth pass, MOVE instruction fetched and
executed.
Condition codes:
Pcr – results of various operations – conditional
branch instructions.
This information – individual bits called
conditional code flags.
These flags – Spl pcr register called status
register or condition code register.
Flag value- 0 or 1 based on operation
performed.
• N (negative) Set to 1 if the result is negative;
otherwise, cleared to 0
• Z (zero) Set to 1 if the result is 0; otherwise,
cleared to 0
• V (overflow) Set to 1 if arithmetic overflow
occurs; otherwise, cleared to 0
• C (carry) Set to 1 if a carry-out results from the
operation; otherwise,cleared to 0
Condition Codes

• Condition code flags

• Condition code register / status register
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
• Different instructions affect different flags
Conditional Branch Instructions
• Example: A: 11110000

• A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
• B: 0 0 0 1 0 1 0 0
11011100

C=1 Z=0

S=1

V=0
Status Bits

Cn-1 A B
Cn
ALU F
V Z S C
Fn-1

Zero Check
Generating memory addresses
Memory operand address – cannot be
given directly in a add instruction
otherwise
Need to be modified on each pass
through the loop.
Suppose Ri holds address of an
operand.
If it is loaded with the address NUM1
& is incremented by 4 on each pass.
Thank You!