Digital Transmission - PCM
Digital Transmission - PCM
Digital Communications
Engr. Rose Anne Reano, PUP-STB
Objectives
• It is important that
the output
impedance of
voltage follower
Z1 and the on
resistance of Q1
be as small as
possible.
PCM Sampling
This ensures that
the RC charging
time constant of the
capacitor is kept
very short, allowing
the capacitor to
charge or
discharge rapidly
during the short
acquisition time.
PCM Sampling
• The rapid drop in
the capacitor
voltage
immediately
following each
sample pulse is
due to the
redistribution of
the charge
across C1.
PCM Sampling
• The interelectrode
capacitance
between the gate
and drain of the
FET is placed in
series with C1 when
the FET is off, thus
acting as a
capacitive voltage-
divider network.
PCM Sampling
• Also, note the
gradual discharge
across the capacitor
during the
conversion time.
PCM Sampling
• This is called droop
and is caused by
the capacitor
discharging through
its own leakage
resistance and the
input impedance of
voltage follower Z2.
PCM Sampling
• Therefore, it is
important that the
input impedance of
Z2 and the leakage
resistance of C1 be
as high as possible.
PCM Sampling
• Essentially, voltage
followers Z1 and Z2
isolate the sample-
and-hold circuit (Q1
and C1) from the
input and output
circuitry.
PCM Sampling
fs ≥ 2fa
where fs minimum Nyquist sample rate (hertz)
fa maximum analog input frequency (hertz)
PCM Sampling
PCM Sampling
DR = Vmax / resolution
2^n - 1 ≥ DR