INSTRUCTION

SET COMPUTING
CHAPTER 4
Objectives:
At the end of this chapter students will be able to:
1. Explain the Instruction Set Architecture.
2. Explain instruction format, addressing modes and types.
3. Discuss interrupts and its types.
4. Compare Instruction Set Architectures.
5. Analyze instruction format, addressing modes and types.
 Instruction Set Architecture (ISA)

• An ISA is defined as the design of a computer

from the Programmer’s Perspective.

• ISA contains multiple pieces that include:

• Addressing modes
• Types of Instructions
• Native data types
• Registers
• Memory architecture
• Interrupt and exception handling,
• External I/O.
Instruction Set Architecture (ISA):

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 Instruction Set Architecture (ISA):

• The instruction set architecture of a

computer defines the various
operations that a computer performs
and the associated instruction
operands.
• Instructions are composed one or
more instruction formats, each
consisting of one or more instruction
fields.
• All instructions will have an
“OPCODE” field.
• There may be zero or more operand
fields.
 Instruction Set Architecture (ISA):
Many modern processors may be based on:
• RISC (Reduced Instruction Set Computer) architecture
designs which use relatively small instruction sets, in contrast to so called
OR
• CISC (Complex Instruction Set Computer) architecture
designs such as the VAX and machines based on the Intel 8086 and
Motorola 68000 microprocessor families.
CISC Architecture
• Complex Instruction Set Computing (CISC) is a CPU design where
single instructions can execute several low-level operations.

• They are also capable of multi-step operations or many addressing

modes within single instructions.

• CISC refers everything from large and complex mainframes to

simplistic microcontrollers where memory load and store operations
are not separated from arithmetic instructions.

• CISC runs and includes full set of instructions in the computer and
uses the microprogrammed control.

• Ex: System/360, Intel 8080 processors are examples of such design.

CISC architecture
RISC Architecture
• Reduced instruction set computing, or RISC is a CPU design
strategy based on the strategy of simplified instruction set

• It provides higher performance when combined with a

microprocessor architecture capable of executing those
instructions using fewer microprocessor cycles per instruction.

• RISC architecture uses a small, highly optimized set of instructions

• RISC systems use the load/store architecture, where memory is

normally accessed only through specific instructions,

• Well-known RISC families include DEC Alpha, AMD 29k, ARC, ARM,
Intel i860.
RISC architecture
RISC vs CISC comparison
Instruction Format
• Instruction format is the function of the control unit within the CPU to
interpret each instruction code.
• The bits of the instruction are divided into groups called fields.
• The most common fields are:
Operation code
Address field – memory address or a processor register.
Mode field – specifies the way the operand or effective address is determined.
• A register address is a binary number of “k” bits that defines one of 2k
registers in the CPU.
• The instructions may have several different lengths containing varying
number of addresses.
• The number of address fields in the instruction format of a computer
depends on the internal organization of its registers.
Instruction Format
• Most computers fall into one of the three following organizations:
Single accumulator organization
General register organization
Stack organization
• Single accumulator organization. uses one address field
ADD X : AC ← AC + M[X]
• The general register organization. uses three address fields
ADD R1, R2, R3: R1 ← R2 + R3
Can use two rather than three fields if the destination is assumed
to be one of the source registers
• Stack organization would require one address field for PUSH/POP
operations and none for operation-type instructions
Classification of Instructions based on Operands
• Zero Operand/Address Instruction
Example: POP
• One Operand/Address Instruction
Example: LOAD A
• Two Operand/Address Instruction
Example: MOV R1, A
• Three Operand/Address Instruction
Example: ADD R1, A, B
 Activity
Identify the length/type of each instruction

Instruction Type

DIV Y, X, R2

LOAD X

ADD

POP X

MUL R1,R2
 Addressing Modes
• The assembly language instructions require the
specification of the location of data for source and
destination operands. The specification of the location
of data is called the addressing mode.

• Addressing modes may be classified as shown in the

following table:
Immediate Addressing
• Immediate addressing means that the data to be used is
hard-coded into the instruction itself.
• This is the fastest method of addressing as it does not
involve main memory at all.
• Immediate Addressing is very useful to carry out
instructions involving constants (as opposed to variables).
For example:
• MOV AL, 25H means move 8-bit data 25H into AL register,
• MOV CX, 23F6H means move 16-bit data 23F6 into CX
register.
• ADD CL, 4BH means add 8-bit data 4BH to CL register.
Direct Addressing
● In this mode the effective address is given in the instruction itself.
This addressing mode also known as Absolute Addressing.

● For example: MOV CL, [1250H] means the CL register will be loaded
with 8-bit data from logical address 1250H.

Other examples
MOV AX, [14ABH] ;Copies the value from address 14ABH into AX
MOV [6023H], AL ;Copies the value from AL into 6023H
MOV [12ABH], DX ;Copies the value from DX into 12ABH and 12ACH (16-
bit data)
Register Addressing
• Most instructions of processors like Intel 8086 can access general
purpose registers.

• This can be done by specifying the name of the register as an operand in

the instruction.
Consider the MOV (move) instruction in 8086:
MOV DESTINATION (Reg), SOURCE(Reg)
• This instruction copies the data from the source operand to the
destination operand.

• Both 8 and 16 bit registers are valid operands for MOV instruction.

• The only restriction is that both operands must be the same size.

Ex: MOV AX, BX ;Copies the value from BX into AX

MOV DL, AL ;Copies the value from AL into DL
MOV SI, DX ;Copies the value from DX into SI
Indirect Addressing
● In this mode of addressing the instruction specifies the register in the CPU
which gives the address of the operand in memory.

● Here the register contents address operator rather than the operand.

● This addressing mode is useful for accessing different memory locations

such as list of consecutive locations. Contents of register can be
incremented after each access to point to the next location.

● Example: MOV CL, [BX] means the register BX contains the address and
the value (data) can be fetched from the memory location (address)
pointed by BX and the same will be copied to CL register.

If the value of BX = 34A9H, and the value at memory location 34A9H = 3EH, the above
instruction will copy the value 3EH to register CL.
Implied Addressing

● The addressing mode of certain instructions is implied

by the instruction's function.
● For example, the STC (SeT Carry flag) instruction deals
only with the carry flag, the DAA (Decimal Adjust
Addition) instruction of Intel 8086 deals with the
accumulator.

● In these types of instructions neither register nor

memory/data is mentioned.
Relative Addressing
It is a kind of indirect addressing. A base register or an index register plus a
displacement are used to indirectly address a data memory. Consider the following
examples,
MOV CL, [BX+30]
MOV [DI-4F0], SP

The displacement will be added or subtracted from the address in the base or index
register temporarily and the original address in them will remain the same. This
enables the program to get data from different areas in memory starting from a fixed
address.

Index Addressing
This is a kind of indirect addressing. One base register is added with one index
register to indirectly address a data memory.

MOV CX, [BX+SI] ;means the BX and SI register contents are added to get the address
and the data at the address is moved to CX register.
MOV [BP+ DI], AH ; means the data from AH register will be stored/moved to
memory location pointed by the addition of BP and DI.
Activity
Give the addressing mode for the following instructions.
a. MOV AX, DS
b. MOV CX, [3000]
c. MOV [BP + 6], AL
d. MOV BX, 3675H
e. MOV AH, [BX + SI + 50]
f. MOV CX, DS
Activity

What will be the contents of the memory location 1210 after execution of
following sets of instructions?

a. MOV BX, 129FH

b. MOV [1210], BX
c. MOV DX, 8C68H
d. MOV [1210], DX
References

1. https://www.geeksforgeeks.org/interrupts-and-exceptions/
2. http://www.computerhope.com/jargon/i/instset.htmRetrieved
http://oozden.wordpress.com/2013/02/08/cisc-architecture-and-ri
sc-architecture
3. http://mydazzling2ndyears.blogspot.com/2013/01/risc-cisc.html
4. http://coitweb.uncc.edu/~abw/ITCS3182F09/slides3.pdf
5. http://en.wikipedia.org/wiki/Reduced_instruction_set_computing
6. http://en.wikipedia.org/wiki/Complex_instruction_set_computing