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Module 2 Instructions

The document introduces the RISC-V architecture, focusing on its instruction set and the stored-program concept, which allows for flexible data and instruction storage in memory. It provides examples of assembly instructions for basic arithmetic operations, data transfer, and logical operations, illustrating how complex statements are broken down into simpler instructions. Additionally, it discusses operand types, overflow, and representation of instructions in binary and hexadecimal formats.

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0% found this document useful (0 votes)
4 views31 pages

Module 2 Instructions

The document introduces the RISC-V architecture, focusing on its instruction set and the stored-program concept, which allows for flexible data and instruction storage in memory. It provides examples of assembly instructions for basic arithmetic operations, data transfer, and logical operations, illustrating how complex statements are broken down into simpler instructions. Additionally, it discusses operand types, overflow, and representation of instructions in binary and hexadecimal formats.

Uploaded by

mrtbsekati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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2.

1 Introduction

• Instruction set
• Instruction set: The vocabulary of commands understood by
a given architecture.
• Stored-program concept
• Stored-program concept: The idea that instructions and data
of many types can be stored in memory as numbers and thus
be easy to change, leading to the stored-program computer.
2.1 Introduction

• Examples
• A simple Add Instruction
ADD A, B, C

This instruction Adds B+C and puts the result in A.

ADD A, B, C
ADD A, A, D
ADD A, A, E
Three Add instructions executes one at a time
2.1 Introduction

• Compiling 2 C assignment statements in RISC V


• a = b + c;
• add a, b, c
• // register a contains b + c

d = a - e;
• sub d, a, e
• // register d contains a - e
2.1 Introduction


f = (g + h) - (i + j);

• add t0, g, h
• // temp t0 contains g + h

• add t1, i, j
• // temp t1 contains i + j

• sub f, t0, t1
• // f gets t0 - t1, which is (g + h) - (i + j)
2.1 Introduction

• A complex statement contains five variables f, g, h, i, and j. The compiler


breaks this statement into several assembly instructions, since only one
operation is performed per assembly instruction.
• The compiler first generates an instruction to calculate g + h, putting the result
in temporary variable t0.
• Although the next operation is subtract, the compiler must calculate the sum of
i and j before the subtract. So, next the compiler generates an instruction to
calculate i + j, putting the result in t1.
• Finally, the compiler generates an instruction to calculate t0 - t1, putting the
result in f.
• For the given values of g, h, i, and j, the instructions put the intermediate result
of 4 + 5 or 9 into t0, and then 2 + 1 or 3 into t1. Finally, 9 - 3 or 6 is put into
register f.
2. 2 RISC V OPERANDS

Name Example Comments


Fast locations for data. In RISC-V,
data must be in registers to
32 registers x0 - x31
perform arithmetic.
Register x0 always equals 0.

Accessed only by data transfer


instructions. RISC-V uses byte
Memory[0], Memory [4], ...., addresses, so sequential word
230 memory words
Memory[4,294,967,292] addresses differ by 4. Memory
holds data structures, arrays, and
spilled registers.
2.3 RISC V INSTRUCTION EXAMPLES
Category Instruction Example Meaning Comments
Three register operands;
Add add x5, x6, x7 x5 = x6 + x7
add
Arithmetic Three register operands;
Subtract sub x5, x6, x7 x5 = x6 - x7
subtract
Add immediate addi x5, x6, 20 x5 = x6 + 20 Used to add constants
Word from memory to
Load word lw x5, 40(x6) x5 = Memory[x6 + 40]
register
Unsigned word from
Load word, unsigned lwu x5, 40(x6) x5 = Memory[x6 + 40]
memory to register
Word from register to
Store word sw x5, 40(x6) Memory[x6 + 40] = x5
memory
Load halfword lh x5, 40(x6) x5 = Memory[x6 + 40] Halfword memory to register
Unsigned halfword memory
Load halfword, unsigned lhu x5, 40(x6) x5 = Memory[x6 + 40]
to register
Halfword from register to
Store halfword sh x5, 40(x6) Memory[x6 + 40] = x5
memory
Data transfer Byte from memory to
Load byte lb x5, 40(x6) x5 = Memory[x6 + 40]
register
Byte unsigned from memory
Load byte, unsigned lbu x5, 40(x6) x5 = Memory[x6 + 40]
to register
Byte from register to
Store byte sb x5, 40(x6) Memory[x6 + 40] = x5
memory
Load; 1st half of atomic
Load reserved lr.d x5, (x6) x5 = Memory[x6]
swap
Store; 2nd half of atomic
Store conditional sc.d x7, x5, (x6) Memory[x6] = x5; x7 = 0/1
swap
2.3 RISC V ASSEMBLY LANGUAGE EXAMPLES

Category Instruction Example Meaning Comments

Three reg. operands; bit-by-bit


And and x5, x6, x7 x5 = x6 & x7
AND
Three reg. operands; bit-by-bit
Inclusive or or x5, x6, x8 x5 = x6 | x8
OR
Three reg. operands; bit-by-bit
Exclusive or xor x5, x6, x9 x5 = x6 ^ x9
Logical XOR
Bit-by-bit AND reg. with
And immediate andi x5, x6, 20 x5 = x6 & 20
constant
Inclusive or immediate ori x5, x6, 20 x5 = x6 | 20 Bit-by-bit OR reg. with constant
Bit-by-bit XOR reg. with
Exclusive or immediate xori x5, x6, 20 x1 = x6 ^ 20
constant
Shift left logical sll x5, x6, x7 x5 = x6 << x7 Shift left by register

Shift right logical srl x5, x6, x7 x5 = x6 >> x7 Shift right by register
Arithmetic Shift right by
Shift right arithmetic sra x5, x6, x7 x5 = x6 >> x7
register
Shift
Shift left logical immediate slli x5, x6, 3 x5 = x6 << 3 Shift left by immediate

Shift right logical immediate srli x5, x6, 3 x5 = x6 >> 3 Shift right by immediate
Shift right logical arithmetic Arithmetic shift right by
srai x5, x6, 3 x5 = x6 >> 3
immediate immediate
2.3 RISC V INSTRUCTION EXAMPLES
Category Instruction Example Meaning Comments

PC-relative branch if registers


Branch if equal beq x5, x6, 100 if (x5 == x6) go to PC + 100
equal

PC-relative branch if registers not


Branch if not equal bne x5, x6, 100 if (x5 != x6) go to PC + 100
equal

Branch if less than blt x5, x6, 100 if (x5 < x6) go to PC + 100 PC-relative branch if registers less

PC-relative branch if registers


Branch if greater or equal bge x5, x6, 100 if (x5 >= x6) go to PC + 100
greater or equal
Conditional branch

PC-relative branch if registers


Branch if less, unsigned bltu x5, x6, 100 if (x5 < x6) go to PC + 100
less, unsigned

Branch if greater or equal, PC-relative branch if registers


bgeu x5, x6, 100 if (x5 >= x6) go to PC + 100
unsigned greater or equal, unsigned

Jump and link jal x1, 100 x1 = PC+4; go to PC + 100 PC-relative procedure call
Unconditional jump
Jump and link register jalr x1, 100(x5) x1 = PC+4; go to x5 + 100 Procedure return; indirect call
2.4 OPERANDS OF THE COMPUTER HARDWARE

• Word
• Word: The natural unit of access in a computer, usually
a group of 32 bits; corresponds to the size of a register
in the RISC-V architecture.
• Doubleword
• Doubleword: Another natural unit of access in a
computer, usually a group of 64 bits.
2.4 OPERANDS OF THE COMPUTER HARDWARE

• Smaller is faster: With fewer registers, the clock


frequency can be made faster, because the clock signal
requires less time to reach every register.

• (A) (B)

A)Clock frequency: 1.4 GHz


B)Clock frequency: 1.2 GHz
2.4 OPERANDS - EXAMPLE
2.4 OPERANDS -
DATA TRANSFER
INSTRUCTIONS

•Data transfer instruction: A


command that moves data
between memory and registers.
•Address
•Address : A value used to
delineate the location of a
specific data element within a
memory array.
•Figure 2.3.1: Memory addresses
and contents of memory at
those locations (COD Figure 2.2).

2.4 OPERANDS- DATA TRANSFER INSTRUCTIONS

• load
The data transfer instruction that copies data from memory
to a register is traditionally called load.
• base address
A base address is the starting address of an array in memory.
• base register
A base register is a register that holds an array's base
address.
• offset
An offset is a constant value added to a base address to
locate a particular array element.
2.4 DATA TRANSFER EXAMPLE BASE REGISTER AND OFFSET
2.4 Alignment restrictions – A requirement that data be aligned in memory on
natural boundariesA requirement that data be aligned in memory on natural boundaries.
2.5Signed and Unsigned Numbers
2.4 Significant and Overflow
• Least significant bit
• Least significant bit: The rightmost bit in a RISC-V word.
• Most significant bit
• Most significant bit: The leftmost bit in a RISC-V word.
• overflow
• If the number that is the proper result of such operations
cannot be represented by these rightmost hardware bits,
overflow is said to have occurred.
• Overflow
• Overflow: when the results of an operation are larger than
can be represented in a register.
2.5 Binary to decimal conversion
2.6Complements
• One's complement
• One's complement: A notation that represents the most negative
value by 10 … 000two and the most positive value by 01 … 11two,
leaving an equal number of negatives and positives but ending up
with two zeros, one positive (00 … 00two) and one negative (11 …
11two). The term is also used to mean the inversion of every bit in a
pattern: 0 to 1 and 1 to 0.
• Biased notation
• Biased notation: A notation that represents the most negative value
by 00 … 000two and the most positive value by 11 … 11two, with 0
typically having the value 10 … 00two, thereby biasing the number
such that the number plus the bias has a non-negative representation.
2.7Representing Instructions in the
Computer

•fields
•A machine instruction is composed of fields, each field having
several bits and representing some part of the instruction.
2.7 Contd
• Instruction format
• Instruction format: A form of representation of an instruction composed of fields of
binary numbers.
• Machine language
• Machine language: Binary representation used for communication within a
computer system.
• Hexadecimal
• Hexadecimal: Numbers in base 16.

• Figure 2.5.1: The hexadecimal-binary conversion table (COD Figure 2.4).


• Just replace one hexadecimal digit by the corresponding four binary digits, and vice
versa. If the length of the binary number is not a multiple of 4, go from right to left.
Assignment
• Read up the following in the main Zybook text:
• We shall discuss the topics in details in class
2.6 Logical operations
2.7 Instructions for making decision
2.8 Supporting procedures in hardware (caller, callee,
stack…)
2.9 Communicating with people (ASCII, Unicode)

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