Module-1

Syllabus
MODULE 1

● BASICS OF TESTING AND FAULT MODELING: Introduction to Testing - Faults in digital circuits -
Modelling of faults - Logical Fault Models - Fault detection - Fault location -Fault dominance -Logic
Simulation - Types of simulation - Delay models - Gate level Event-driven simulation.
IMPORTANCE OF TESTING

● The feature size of an Integrated Circuit (IC) refers to the smallest dimension of a component or structure
(such as a transistor gate, interconnect, or other elements) that can be fabricated on a semiconductor chip.

● It is often expressed in nanometers (nm) or micrometers (µm) and directly influences the performance, power
consumption, and density of the IC.

● The reduction in feature size increases the probability that a manufacturing defect in the IC will result in a
faulty chip. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature
size is less than 100nm.

● Furthermore, it takes only one faulty transistor or wire to make the entire chip fail to function properly or at
the required operating frequency.

● Yet, defects created during the manufacturing process are unavoidable, and, as a result, some number of ICs
is expected to be faulty; therefore, testing is required to guarantee fault free products, regardless of whether
the product is a VLSI device or an electronic system composed of many VLSI devices.
Failures and Faults

1.Failure:
• Occurs when a circuit/system deviates from its specified behavior.
2.Fault:
• A physical defect that may or may not cause a failure.
• Characterized by nature, value, extent, and duration.
3.Nature of Faults:
• Logical Fault: Causes a logic value to flip to the opposite state.
• Nonlogical Fault: Includes issues like clock signal malfunction, power failure, etc.
4.Value of a Logical Fault:
• Can be fixed or varying erroneous logical values.
5.Extent of Faults:
• Local Fault: Affects a single variable (e.g., logical fault).
• Distributed Fault: Affects multiple components (e.g., clock malfunction).
6.Duration of Faults:
• Permanent Fault: Lasts indefinitely.
• Temporary Fault: Occurs for a short time.
A circuit error is a wrong output signal produced by a defective circuit. A circuit defect may
lead to a fault, a fault can cause a circuit error, and a circuit error can result in a system
failure.

To test a circuit with n inputs and m outputs, a set of input patterns is applied to the circuit
under test (CUT), and its responses are compared to the known good responses of a fault-free
circuit. Each input pattern is called a test vector.

If the CUT is an n-input combinational logic circuit, we can apply all 2n possible input patterns
for testing stuck-at faults; this approach is called exhaustive testing.

Applying all possible input test patterns to an n-input combinational logic circuit also
illustrates the basic idea of functional testing, where every entry in the truth table for the
combinational logic circuit is tested to determine whether it produces the correct response.

Practical approach is to select specific test patterns based on circuit structural information and
a set of fault models. This approach is called structural testing. Structural testing saves time
and improves test efficiency, as the total number of test patterns is decreased because the
test vectors target specific faults that wouldresultfromdefectsinthemanufacturedcircuit.
Fault Coverage in VLSI Testing

Fault coverage is a key metric in VLSI (Very Large Scale Integration) testing that measures the effectiveness of test
patterns in detecting faults in a circuit. It is defined as:

Higher fault coverage ensures that more faults are detected, reducing the risk of manufacturing defects in semiconductor
chips.
Any input pattern, or sequence of input patterns, that produces a different output response in
a faulty circuit from that of the fault-free circuit is a test vector,or sequence of test vectors,
that will detect the faults. The goal of test generation is to find an efficient set of test vectors
that detects all faults considered for that circuit.
Modelling of Faults
Causes of Faults in Circuits:
▪ Defective components
▪ Breaks in signal lines
▪ Short-circuiting of signal lines
▪ Lines shorted to ground or power supply
▪ Excessive delays
▪ Errors in design specifications
▪ Design rule violations
Fault Representation:
• A fault is modeled based on the change it produces in circuit signals.
Common Fault Models:
1.Stuck-at Fault – Signal remains fixed at logic ‘1’ or ‘0’.
2.Bridging Fault – Unintended connection between two signal lines.
3.Stuck-open Fault – A node fails to establish a connection when required.
Stuck-at Faults:

● Single stuck-at fault: Assumes that a fault in a logic gate result in one of its inputs or the output being fixed to
either a logic 0 (stuck-at-0) or a logic 1 (stuck-at-1).
● Multiple stuck-at fault: assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0; in
other words, a group of stuck-at faults exist in the circuit at the same time

● Example - NAND Gate with s-a-1 Fault:

● Faulty input A (s-a-1):
• NAND perceives A as 1, regardless of actual input.
• Results in an incorrect output compared to a fault-free gate.
● Testing for Stuck-at Fault:
• A test pattern is used to compare faulty and fault-free outputs.
● Significance of Stuck-at Fault Model:
● Referred to as the classical fault model.
● Represents common failures like:
• Short circuits (shorts)
• Open circuits (opens)
CMOS (Complementary Metal Oxide Semiconductor) realization of a NAND gate
●
Bridging Faults
Definition:
Bridging faults occur due to unintended shorts between two or more signal lines in VLSI circuits.
These faults cannot be modeled as simple stuck-at faults.

Causes:
•Increased device density in VLSI chips.
•Physical defects in MOS circuits.

Types of Bridging Faults:

1.Input Bridging: Shorting of two or more primary input lines.

2.Feedback Bridging: Short between an output and an input line.
3.Non-Feedback Bridging: Shorts that do not belong to the first two categories.

Behavior of Bridging Faults:

•Positive Logic: Behaves as a wired-AND (0 is dominant).
•Negative Logic: Behaves as a wired-OR (1 is dominant).
 Bridging fault
A short between two elements is commonly referred to as a bridging fault.

These elements can be transistor terminals or connections between transistors and gates. The
case of an element being shorted to power (VDD) or ground (VSS) is equivalent to the stuck-at
fault model; however, when two signal wires are shorted together, bridging fault models are
required.

In the first bridging fault model proposed, the logic value of the shorted nets was modeled as a
logical AND or OR of the logic values on the shorted wires. This model is referred to as the
wired-AND/wired-OR bridging fault model.

The wired-AND bridging fault means the signal net formed by the two shorted lines will take on
a logic 0 if either shorted line is sourcing a logic 0, while the wired-OR bridging fault means the
signal net will take on a logic 1 if either of the two lines is sourcing a logic 1.

Therefore, this type of bridging fault can be modeled with an additional AND or OR gate, as
illustrated in Figure 1.9a, where AS and BS denote the sources for the two shorted signal nets
and AD and BD
BREAKS AND TRANSISTOR STUCK-ON/-OPEN FAULTS IN CMOS

CMOS circuits can experience breaks or opens due to missing conducting material or extra insulating material.
These breaks can be classified into:

● Intragate Breaks
● Signal Line Breaks

Intragate Breaks
Occur within a gate, disconnecting the source, drain, or gate of a transistor.
Identified in Fig. 1.9 at positions b₁, b₂, and b₃.

Effects of Intragate Breaks

Break Effect

b₁ Increases propagation delay (delay fault)

b₂ Makes the p-transistor nonconducting (stuck open)

b₃ Causes a delay fault without altering circuit function

● Breaks can also disconnect the p-network or n-network at b₄, b₅, b₆.
○ b₄: Output stuck-at-0.
○ b₅: Output stuck-at-1.
○ b₆: Intermittent stuck-at-0 or stuck-at-1, causing unpredictable behavior.

Signal Line Breaks

● Occur when a transistor gate is left floating due to disconnection.
● Can affect:
○ Only a p-transistor
○ Only an n-transistor
○ Both transistors, leading to unexpected conduction/non-conduction.

Effects of Signal Line Breaks

● Modeled as stuck-at faults.
● If two transistors float:
○ One may be permanently conducting (stuck-on).
○ One may be permanently nonconducting (similar to intragate break b₂).
Stuck-On and Stuck-Open Faults in CMOS
Circuits (Transistor Faults)
Introduction to Transistor-Level Faults
● CMOS circuits should be tested for shorts (stuck-on faults) and opens (stuck-open faults) at the transistor level.
● Stuck-On Fault: A transistor remains permanently conducting (closed).
● Stuck-Open Fault: A transistor remains permanently non-conducting (open).
● Detecting these faults is crucial as they can alter circuit behavior.

Stuck-On Faults (Shorts)

● Definition: Permanent connection between the source and drain of a transistor.
● Characteristics:
○ Similar to a stuck-closed transistor but has normal on-resistance.
○ Can be modeled as a bridging fault (unintended short circuit).
○ Impact: Can lead to logic errors and excessive power dissipation.
○ Occurrence: Estimated 10–13% of CMOS faults.
Stuck-Open Faults (Opens)
● Definition: Permanent disconnection between the source and drain.
● Characteristics:
○ The transistor behaves as if it is always turned off.
○ Causes floating output nodes, leading to state retention issues.
○ Impact: Turns a combinational circuit into a sequential circuit (state depends on leakage current).
○ Occurrence: About 1% of CMOS faults.
○ Example: If transistor T₂ is stuck-open in a CMOS NOR gate, the output retains its previous logic state.
Stuck-Open Fault and Short Faults in a CMOS NOR Gate
 Delay Faults in VLSI Circuits:Understanding Timing-Related Defects in CMOS Circuits

Introduction to Delay Faults

● Traditional stuck-at fault models do not cover all manufacturing defects in VLSI circuits.
● Smaller defects (due to process variations) may not change logic functionality but impact timing.
● These defects slow down signal transitions (0 → 1 or 1 → 0), causing timing failures.
● This type of malfunction is referred to as a delay fault.

. Importance of Delay Fault Testing

● Functional testing may not detect delay faults.
● Specialized delay testing techniques are needed:
○ Launch-on-Capture (LOC)
○ Launch-on-Shift (LOS)
○ Path Delay Testing
● Ensures circuits meet timing specifications across process, voltage, and temperature (PVT) variations.
Gate Delay Fault
● Definition: The propagation delay of a faulty gate exceeds its worst-case specification.
● Example:
○ A gate with a worst-case delay of x units now has a delay of x + Δx units.
○ The fault size is represented as Δx.
● Limitations:
○ Only models isolated defects (not multiple distributed defects).

B. Path Delay Fault

● Definition: A fault occurs when the total delay along a circuit path exceeds its allowed limit.
● Advantages:
○ Can model both isolated and distributed defects.
○ More practical for testing complex circuits with multiple delay sources.
Temporary Faults in Digital Systems

Asignificant portion of digital system malfunctions is caused by temporary faults. These faults contribute to over
90% of total maintenance expenses due to their challenging detection and isolation

Types of Temporary Faults

Temporary faults are often categorized as intermittent or transient faults.

Transient Faults
○ Nonrecurring and temporary in nature.
○ Caused by external factors such as α-particle radiation or power supply fluctuations.
○ Do not cause physical damage and are not repairable.
○ Major source of failures in semiconductor memory chips.
● Intermittent Faults
○ Recurring faults that reappear periodically.
○ Caused by factors such as loose connections, partially defective components, or poor designs.
○ Can be aggravated by aging components, eventually becoming permanent.
○ Environmental factors like temperature, humidity, and vibration also contribute.
○ The likelihood of occurrence depends on protective measures (shielding, filtering, cooling).
 Controllability and Observability
Controllability:
In order to generate a test a for a stuck-at fault on a signal line, it must first be forced to a value
that is opposite to the stuck-at value on the line.
This ability to apply input patterns to the primary inputs of a circuit to set up appropriate logic
value at desired locations of a circuit is known as Controllability.
For example, in the presence of a stuck-at-0 fault, the location of the fault must be set to logic 1
via the primary inputs; this is known as 1-controllability.
Similarly, for a stuck-at-1 fault, the location of the fault must be set to logic 0 to excite the fault;
this is known as 0-controllability.
Observability:
Test generation process requires application of appropriate input values at the primary inputs so
the effect of the fault is observable at the primary outputs.
The ability to observe the response of a fault on an internal node via the primary outputs of a
Undetectable Faults
A fault is considered to be undetectable if it is not possible
to activate the fault or to sensitize its effect to primary
outputs.
In other words, a test for detecting the fault does not exist.
To illustrate, let us consider the α s-a-0 fault shown in
Figure 1.10.
It is not possible to set the node α to logic 1. Therefore,
the fault cannot be excited and thus undetectable.
The fault β s-a-0 can be excited by making ab=10, but no
sensitized path is available for propagating the effect of
the fault to the output; hence, the fault is undetectable.
A combinational circuit is denoted as redundant if it has
an undetectable fault.
MODULE-2
Fault Detection in Logic Circuits
● Objective of Testing:

○ Ensure proper functionality of logic gates and interconnections.

○ Detect faults using a minimal test set.

● Challenges in Testing:

○ Combinational Circuits: Require 2ⁿ test combinations, which grow exponentially.

○ Sequential Circuits: Require 2^(n+m) tests (n inputs, m flip-flops), making exhaustive testing impractical.
● Example:

○ For n=20, m=40 → 2⁶⁰ tests.

○ At 10,000 tests/sec → 3.65 million years to complete!
● Fault Coverage:

○ Measures the percentage of detectable faults.

○ Test generation time ∝ (Number of Gates)².
○ Sequential circuits pose higher complexity due to exponential memory states.
● Conclusion:

○ Efficient test pattern selection is crucial for detecting faults without exhaustive testing.
TEST GENERATION FOR COMBINATIONAL LOGIC CIRCUITS
Method for fault detection in a combinational circuit using a truth table and fault matrix approach.

The most straightforward method for generating tests for a particular fault is to compare the re sponses of the fault-free and the
faulty circuit to all possible input combinations.

Any input combination for which the output responses do not match is a test for the given fault.

Note: α s-a-0 and β s-a-l.

The minimum number of tests required to detect a set of faults in a combinational circuit can be obtained
from a fault matrix.
These four tests
detect all of the
six faults under
consideration.

Figure 2.2: (a) Circuit under test. (b) Fault matrix. (c) Minimal test set.
From this example that the fault matrix approach to test generation is not practicable when
the number of input variables is large.

We now discuss some alternative techniques developed to solve test generation problems.

Path Sensitization
Path Sensitization
Refer Class Notes
fault α s-a-0
D-Algorithm

● The D-algorithm is guaranteed to find a test if one exists for detecting a

fault.
● The D-algorithm is used in fault detection by representing both good and
faulty circuit values.
● Generate Test Pattern for non-redundant combinational circuit.
● Fewer terms need to be known, before understanding D-Algorithm.

1. Singular Cover
2. Propagation D-Cube
3. Primitive D-Cube
Singular Cover
● Singular Cover of logic
gate is a compact form of
truth table

● Each row in singular cover

is termed as “Singular
Cube”.
 Propagation D-cube

● The propagation D-cubes of a gate are those that cause the output of the gate to depend only on one or
more of its specified inputs.
● Thus, a fault on a specified input is propagated to the output.
● "D" represents a discrepancy signal, indicating a node in a circuit that exhibits a different value under
faulty conditions compared to its normal, non-faulty state.
● Discrepancy Signal:
The "D" signal signifies that a node's value is different when a fault (e.g., a stuck-at-0 or stuck-at-1
fault) is present compared to when the circuit is operating normally.
● The D-algorithm uses a notation where 'D' represents a node that is 0 under normal conditions and 1
under faulty conditions, and 'D complement' (often denoted as D') represents a node that is 1 under
normal conditions and 0 under faulty conditions.
The propagation D-cube of a three-input NOR gate can be formed as shown in Figure 2.7
 Primitive D-cube of a fault
The primitive D-cube of a fault (pdcf) is used to specify the existence of a given fault.
It consists of an input pattern which shows the effect of a fault on the output of the gate.
For example, if the output of the NOR gate shown in Figure 2.6 is s-a-0, the corresponding pdcf is:

Here, D is interpreted as being 1 if the circuit is fault-free and is 0 if the fault is present. The
pdcf’s for the NOR gate output s-a-1 are:
Let us consider a three-input NAND gate with input lines a, b, and c and output line f. The singular cubes for
the fault-free NAND gate are:
D-Algorithm
Let us next consider how the various cubes described are used in the D-algorithm method to
generate a test for a given fault. The test generation process consists of three steps:
Step 1: Select a pdcf for the given fault.
Step 2: Drive the D (or D’ ) from the output of the gate under test to an output of the circuit by
successively intersecting the current test cube with the propagation D-cubes of successive gates. A
test cube represents the signal values at various lines in the circuit during each step of the test
generation process. The intersection of a test cube with the propagation D-cube of a successor gate
results in a test cube.
Step 3: Justify the internal line values by driving back toward the inputs of the circuit, assigning
input values to the gates so that a consistent set of circuit input values may be obtained.
D-Algorithm Steps

● Choose a stuck-at-fault at any of the nodes.

● Choose a pdcf for generating the fault.
● Choose an output and a path to the output and propagate the fault to the output by
choosing pdc for all circuit elements on the path. (D-Drive)
● Use the SC of all unassigned circuit elements to arrive at a consistent set of inputs.
(back-propagate or consistency check).
Let us demonstrate the application of the D-algorithm by deriving a test for
detecting the α s-a-0 fault in the below Figure

Solution: Solved in Class

 Let us demonstrate the application of the D-algorithm by deriving a test for
detecting the α s-a-1 fault in Figure 2.8a. The test generation process is
explained in Figure 2.8b.

Figure 2.8a.
Solution: Solved in
Class

The consistency operation at step 4 terminates unsuccessfully because the output of G3 has to be set to 1.
This can be done only by making input B=0; however, B has already been assigned 1 in step 1.
A similar problem will arise if D is propagated to the output via G3 instead of G2.

Note: Any D- Cube that represents a partially formed test during D-Drive is called ‘test cube’.
The only way the consistency problem can be resolved is if the D output of G1 is propagated to the output of
the circuit via both G2 and G3 as shown in Figure 2.8c. No consistency operation is needed in this case, and
the test for the given fault is AB=11. This test also detects the output of G2 s-a-0, the output of G3 s-a-0, and
the output of G4 s-a-1.
Assignment:1) Find Test Vector using D-Algorithm

Answer: Test Vector: 1010

Assignment:2) Find Test Vector using D-Algorithm

Answer: Test Vector: 100

Find Test Vector using D-Algorithm

Answer: Test Vector:

0X111X