Basic Computer Organization & Design 1

BASIC COMPUTER ORGANIZATION AND DESIGN

• Instruction Codes

• Computer Registers &

STORED PROGRAM ORGANIZATION

• Computer Instructions

• Timing and Control

• Instruction Cycle

• Memory Reference Instructions

• Input-Output and Interrupt

• Complete Computer Description

• Design of Basic Computer

• Design of Accumulator Logic

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 2

THE BASIC COMPUTER

• The Basic Computer has two components, a processor and memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
• Every different processor has its own design (different registers, buses, micro-operations,
machine instructions, etc). Modern processor is a very complex device
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating point calculations
– The ability to pipeline several consecutive instructions to speed execution etc.
CPU RAM
0

15 0

Basic computer with processor & memory

4095

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 3 Instruction codes

INSTRUCTIONS

• Program
– A sequence of (machine) instructions
• (Machine) Instruction or microinstruction:
– a sequence of micro-operation that tell the computer to perform a
specific operation is called microinstruction.
• The instructions of a program, along with any needed data
are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the
instruction into the sequence of micro operations
necessary to implement it

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 4

Microinstruction and Micro operation

 In computer CPU, Micro-operations are low-level instructions used in some designs to
implement complex machine instructions.
 Micro-operation is the most basic operation achievable by a processor; i.e.,
Micro-operations perform basic operations on data stored in one or
more registers, including transferring data between registers or between registers and
external buses of the CPU, and performing arithmetic or logical operations on registers.
In a typical fetch-decode-execute cycle, each step of a micro-instruction is
decomposed during its execution so the CPU determines and steps through a series of
micro-operations. The execution of micro-operations is performed under control of the
CPU's control unit, which decides on their execution while performing various
optimizations.

 Microinstruction: an instruction stored in control memory.

A micro-instruction is a set of micro-operations which are executable simultaneously.
A symbolic microprogram can be translated into its binary equivalent by means of an assembler.
Each line of the assembly language microprogram defines a symbolic microinstruction.

 Microprogram: Sequence of microinstructions.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 5

Instruction Code: An instruction code is a group of bits that instruct

the computer to perform a specific operation.

Operation Code: The operation code of an instruction is a group of

bits that define such operations as add, subtract, multiply, shift, and
complement.
The number of bits required for the operation code of an
instruction depends on the total number of operations available in the
computer. The operation code must consist of at least n bits for a given
2^n (or less) distinct operations. Ex: for 64 distinct operations, the
operation code consists of 6 bits (2^6).

Accumulator (AC): Computers that have a single-processor register

usually assign to it the name accumulator (AC) accumulator and label
it AC. The operation is performed with the memory operand and the
content of AC.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 6

Stored Program Organization

The simplest way to organize a computer is to have
one processor register and an instruction code format
with two parts.
 The first part specifies the operation to be
performed and the second specifies an address.
 The memory address tells the control where to find
an operand in memory.
 This operand is read from memory and used as the
data to be operated on together with the data stored in
the processor register.
The following figure 2.1 shows this type of
organization.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 7

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 8

STORED PROGRAM ORGANIZATION (CONTINUED…)

Instructions are stored in one section of memory and data in another.

 For a memory unit with 4096 words, we need 12 bits to specify an
address since 2^12 = 4096.
If we store each instruction code in one 16-bit memory word, we have
available four bits for operation code (abbreviated opcode) to specify one
out of 16 possible operations, and 12 bits to specify the address of an
operand.
 The control reads a 16-bit instruction from the program portion of
memory. It uses the 12-bit address part of the instruction to read a 16-bit
operand from the data portion of memory.
it then executes the operation specified by the operation code.
 Computers that have a single-processor register AC.
 If an operation in an instruction code does not need an operand from
memory, the rest of the bits in the instruction can be used for other
purposes. For example, operations such as clear AC, complement AC,
and increment AC operate on data stored in the AC register. They do not
need an operand from memory. For these types of operations, the second
part of the instruction code (bits 0 through 11) is not needed for specifying
a memory address and can be used to specify other operations for the
computer.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 9 Instruction codes

BASIC INSTRUCTION FORMAT

• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for
that instruction
– An address that specifies the registers and/or locations in
memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address.
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode
• It consists of a 3-bit operation code, a 12-bit address, and an I bit.
• If I=0,Direct address;if I=1,Indirect address.

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 10 Instruction codes

ADDRESSING MODES
• The address field of an instruction can represent either
– Direct address: the address in memory of the data to use (the address of the
operand), or
– Indirect address: the address in memory of the address in memory of the data to
use
A direct address instruction is shown in Figure 2.1 Direct addressing Indirect addressing
– It is placed in address 22 in memory.
– if (MSB) I bit is 0, a direct address instruction. 22 0 ADD 457 35 1 ADD 300
– The opcode specifies an ADD instruction, and
the address part is the binary equivalent of 457.
– The control finds the operand in memory 300 1350
at address 457 and adds it to the content of AC.
457 Operand
An indirect address instruction is shown in Figure 2.2
– if (MSB) I bit is 1, an indirect address instruction. 1350 Operand
– It is placed in address 35 in memory
– The address part is the binary equivalent of 300.
– The control goes to address 300 to
find the address of the operand.
– The address of the operand in this
case is 1350.
+ +
– The operand found in address 1350
is then added to the content of AC. AC AC

• Effective Address (EA)

– The address, that can be directly used without modification to access an operand for a
computation-type instruction, or as the target address for a branch-type instruction.
– This EA IS 457 IN DIRECT & 1350 IN INDIRECT ADDRESS.
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 11

COMPUTER ORGANIZATIONS
 Generally CPU organization are of three types on the
basis of number of address fields:

• Single Accumulator organization: In this organization

operation is done involving a special register called
accumulator.

• General register organization: In this,multiple

registers are used for the computation purpose.

• Stack organization: the work on stack basis

operation due to which it does not contain any
address field.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 12

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 13

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 14

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 15 Registers

BASIC COMPUTER REGISTERS

Registers in the Basic Computer

11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 16 Instruction codes

computer REGISTERS
• It is necessary to provide a register in the control unit for
storing the instruction code after it is read from memory.
• The computer needs processor registers for manipulating data
and a register for holding a memory address.
• In a direct or indirect addressing, the processor needs to keep
track of what locations in memory it is addressing: The
Address Register (AR) is used for this
– The AR is a 12 bit register in the Basic Computer
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register –
the Accumulator (AC)

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 17 Instruction codes

Computer REGISTERS
• The instruction read from memory is placed in the instruction
register (IR).
• The temporary register (TR) is used for holding temporary data
during the processing.
• The memory address register (AR) has 12 bits.
• The program counter (PC) also has 12 bits and it holds the
address of the next instruction to be read from memory after the
current instruction is executed.
• Instruction words are read and executed in sequence unless a
branch instruction is encountered.
• Two registers are used for input and output:
The input register (INPR) receives an 8-bit character from an
input device.
The output register (OUTR) holds an 8-bit character for an output
device.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 18 Registers

COMMON BUS SYSTEM

• The basic computer has eight registers, a memory unit and a control unit.
• Paths must be provided to transfer information from one register to another and
between memory and register.
• The number of wires will be excessive if connections are between the outputs of each
register and the inputs of the other registers. An efficient scheme for transferring
information in a system with many register is to use a common bus.
• The connection of the registers and memory of the basic computer to a common bus
system is shown in figure 3 in next slide.
• The outputs of seven registers and memory are connected to the common bus.
• The specific output that is selected for the bus lines at any given time is determined
from the binary value of the selection variables S2, S1, and S0.
• More efficient scheme for transferring information in a system with many registers.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 19 Registers

COMMON BUS SYSTEM

S2
S1 Bus Common bus is connected to the
S0
inputs of each registers and to
Memory unit 7
4096 x 16 memory.
Address Memory receives the contents of the
Write Read bus when its write input is activated .
The memory places its 16-bit o/p on to
AR 1 the bus when read input is activated

LD INR CLR and s2,s1,s0=111.

the input data and output data is
PC 2 connected to common bus and

LD INR CLR memory address is connected to AR.

Therefore AR specify memory
DR 3 address.
The content of any register can be
LD INR CLR specified for data input during write
E operation and any register receives
ALU AC 4 the data from memory after read
operation.
LD INR CLR 4 Registers DR,AC,IR and TR have 16
bits each. Two registers AR & PC are
INPR 12 bit each since they hold a memory
address. When the contents of AR or
IR 5
PC are applied to 16 bit common bus,
LD the 4 MSB’s are set to 0. When AR or
TR 6 PC receive information from the bus,
only 12 bits are transferred into the
LD INR CLR register.
OUTR
Clock
LD
16-bit common bus

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 20 Registers

COMMON BUS SYSTEM

• Three control lines, S2, S1, and S0 determines which
register the bus selected as its input
S2 S 1 S 0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory

• Ex:Two micro operations DR AC and AC DR can be

executed at the same time. This can be done by placing the
content of AC on the bus(with s2s1s0=100). Enabling the
LD input of DR, transferring the content of DR through the
adder and logic circuit into AC and enabling the load input
AC ,all during the same clock cycle.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 21 Instructions

THREE COMPUTER INSTRUCTIONS FORMATS

• Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 22 Instructions

BASIC COMPUTER INSTRUCTIONS

Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory Memory reference instructions
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E Register reference instructions
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag I/O instructions
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 23 Instructions

INSTRUCTION SET COMPLETENESS

Set of instructions using which user can construct machine
language programs to evaluate any computable function.

• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA (other than ADD/AND?)
Transfer Instructions
- Data transfers between the main memory
and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/Output Instructions
- Input and output
- INP, OUT

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 24 Instruction codes

CONTROL UNIT

• Control unit (CU) of a processor translates from machine

instructions to the control signals (for the microoperations)
that implement them

• Control units are implemented in one of two ways

• Hardwired Control
– CU is made up of sequential and combinational circuits to generate the
control signals
• Microprogrammed Control
– A control memory on the processor contains(stored in a control
memory) that activate the necessary control signals

• We will consider a hardwired implementation of the control

unit for the Basic Computer

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 25 Timing and control

TIMING AND CONTROL

Control unit of Basic Computer

Instruction register (IR)

15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 26 Timing and control

TIMING SIGNALS
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 27

INSTRUCTION CYCLE

• In Basic Computer, a machine instruction is executed in the

following cycle:
1. Fetch an instruction from memory
2. Decode the instruction and calculate effective address (EA)
3. Read the EA from memory if the instruction has an indirect address
(Fetch operand)
1. Execute the instruction

• After an instruction is executed, the cycle starts again at

step 1, for the next instruction

• Note: Every different processor has its own (different)

instruction cycle

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 28 Instruction Cycle

FETCH and DECODE

• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 Micro operations for fetch &

The micro operation S2 decode phases can be specified
for indirect by register transfer statements.
T0 S1 Bus
address is AR
M[AR]. At time T0,
S0
AR holds the Initially, PC is loaded with the
address Part of Memory address of first instruction.
7
instruction.
unit since only AR is connected to
This Address is Address address input of memory, it is
Read necessary to transfer the
used in Memory
read operation. address from PC to AR at T0 by
The word at the making s2s1s0=010.
AR 1
address given by
AR is read from At time T1,
LD 1.Enable the read input from
memory and
placed on Common PC 2 the memory.
bus. 2.Place the content of memory
The LD Input of AR onto the bus by making
INR
is Activated to s2s1s0=111.
receive indirect 3.Tranfer the content of the bus
IR 5 to IR by enabling the LD input
address.
of IR.
LD Clock 4.Increment PC by enabling INR
Common bus input of PC
At time T2, IR is decoded

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 29 Instrction Cycle

DETERMINE THE TYPE OF INSTRUCTION

Start
SC 

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14), During time T3, control unit determines the
AR  IR(0-11), I  IR(15) type of instruction that was just read from
memory as shown in flowchart.
(Register or I/O) = 1 = 0 (Memory-reference) =>opcode ≠ 111
D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 30 Instruction Cycle

REGISTER REFERENCE INSTRUCTIONS

Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T 3

r = D7 IT3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 31

Where D7IIT3: execute register -reference instructions designated as symbol r &

Control function is distinguish by IR(0-11) designated as symbol B, then all
control functions can de denoted by rBi.
Ex: The instruction CLA has the hexadecimal code 7800 gives, binary equivalent
0111 1000 0000 0000.
The first bit is 0 equivalents to II.
Next three bits represents the opcode from decoder output D 7.
Bit 11 in IR is 1 and recognized from B11.
The control function that initiates the micro operation for this instruction is D 7IIT3B11.
i.e.,rB11=D7IIT3B11
 The execution of register reference instruction is completed at time T 3 when D7 bit is
active from decoder. SC cleared to 0 and control goes back to fetch the
next instruction with timing signal T0.
 The first seven register-reference instructions perform clear, complement,
circular shift and increment micro operations on the AC or E registers.
Next four instructions cause a skip of next instruction with condition.
The AC is positive/negative based on MSB bit.
AC is 0 if all the flip-flops of registers are zero.
The HLT instruction clears a start-stop flip-flop S and stops the SC from counting.

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 32 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1
- The effective address of the instruction is in AR and was placed there during
timing signal T2 when I = 0, or during timing signal T 3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T 4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC
ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 33

MEMORY REFERENCE INSTRUCTIONS

LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory Memory

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 34 MR Instructions

MEMORY REFERENCE INSTRUCTIONS

BSA:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 35 MR Instructions

FLOWCHART FOR MEMORY REFERENCE INSTRUCTIONS

Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4
PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 36 I/O and Interrupt

INPUT-OUTPUT CONFIGURATION
A Terminal with a keyboard and a Printer
• Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI
INPR Input register - 8 bits
OUTR Output register - 8 bits Serial Communications Path
FGI Input flag - 1 bit Parallel Communications Path
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

- The terminal sends and receives serial information

- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 37

INPUT-OUTPUT INSTRUCTIONS
CPU Side: input-output instructions are needed for transmitting information to/from AC.

Designed by RTL condition: D7IT3 = p(symbol let say)

IR(i) = Bi, i = 6, …, 11

p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 38 I/O and Interrupt

INPUT-OUTPUT DEVICES HANDLING/ACCESING:

• Computer can do operations if it can communicate with external environment
(through I/O).
•Instructions in the memory or in registers placed by INPUT devices.
•Output IS SHOWN through output devices.
Input-output
- devices can be handling/accessed by CPU in three ways:
1.Program-controlled I/O: This method controls the transfer of data between I/O
devices & CPU.
-Each I/O device is connected to computer for checking inputs.
-Once CPU receive the input signal from Input device, it executes it completely
and then takes the next I/O request.
-CPU Involves totally as it has to see each & every input request from I/O device.
Delay increases.
2.INTERRUPT INITIATED INPUT/OUTPUT: controls the data transfer to/from I/O.
It allows the CPU to continue to do its work & will be interrupted only when it
receives an input signal from an I/O device. delay decreases and throughput
increases.
3.DMA :No involvement of CPU.DMA WILL CONTROL ALL OPERATIONS
OF I/O ITSELF.
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 39

INTERRUPT INITIATED INPUT/OUTPUT

- Open communication only when some data has to be passed --> interrupt.

- The I/O interface, instead of the CPU, monitors the I/O device.

- When the interface founds that the I/O device is ready for data transfer,
it generates an interrupt request to the CPU

- Upon detecting an interrupt, the CPU stops momentarily the task

it is doing, branches to the service routine to process the data
transfer, and then returns to the task it was performing.

* IEN (Interrupt-enable flip-flop)

- can be set and cleared by instructions

- when cleared, the computer cannot be interrupted

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 40 I/O and Interrupt

FLOWCHART FOR INTERRUPT CYCLE

Instruction cycle =0 =1 Interrupt cycle
R

Fetch and decode Store return address

instructions in location 0 IEN : Interrupt enable flip-flop
M[0]  PC R: Interrupt flip-flop

Execute =0
IEN
instructions
=1 Branch to location 1
PC  1
=1
FGI
=0
=1 IEN  0
FGO R0
=0
R1

- The interrupt cycle is a HW implementation of a branch

and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 41 Description
COMPLETE COMPUTER DESCRIPTION
Flowchart of Operations
start
SC  0

=0(Instruction =1 (interrupt
R
Cycle) Cycle)
R’T0 RT0
AR  PC AR  0, TR  PC
R’T1 RT1
IR  M[AR], PC  PC + 1 M[AR]  TR, PC  0
R’T2 RT2
AR  IR(0~11), I  IR(15) PC  PC + 1, IEN  0
D0...D7  Decode IR(12 ~ 14) R  0, SC  0

=1(Register or I/O) =0(Memory Ref)

D7

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I
=0
IEN
=1
D7IT3 D 7I’T3 D7’IT3 D 7’I’T3
Execute AR <- M[AR] Idle =1
Execute FGI
I/O RR =0
Instruction Instruction =1
Execute MR D7’T4 FGO
Instruction =0
R1

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 42 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations
Fetch RT0: AR  PC
RT1: IR  M[AR], PC  PC + 1
Decode RT2: D0, ..., D7  Decode IR(12 ~ 14),
AR  IR(0 ~ 11), I  IR(15)
Indirect AR  M[AR]
D7IT3:
Interrupt
T0T1T2(IEN)(FGI + FGO): R1
AR  0, TR  PC
RT0: M[AR]  TR, PC  0
RT1: PC  PC + 1, IEN  0, R  0, SC  0
Memory-ReferenceRT2:
AND DR  M[AR]
D0T4: AC  AC  DR, SC  0
ADD D0T5: DR  M[AR]
D1T4: AC  AC + DR, E  Cout, SC  0
LDA DR  M[AR]
D1T5:
AC  DR, SC  0
STA D2T4:
M[AR]  AC, SC  0
BUN D2T5: PC  AR, SC  0
BSA D3T4: M[AR]  PC, AR  AR + 1
D4T4: PC  AR, SC  0
ISZ D5T4: DR  M[AR]
D5T5: DR  DR + 1
D6T4: M[AR]  DR, if(DR=0) then (PC  PC + 1),
D6T5: SC  0
D6T6:

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 43 Description
COMPLETE COMPUTER DESCRIPTION
Microoperations

Register-Reference
D7IT3 = r (Common to all register-reference instr)
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA AC  0
rB11:
CLE E0
CMA rB10:
AC  AC
CME rB9: E  E
CIR rB8: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB7: AC  shl AC, AC(0)  E, E  AC(15)
INC rB6: AC  AC + 1
SPA rB5: If(AC(15) =0) then (PC  PC + 1)
SNA rB4: If(AC(15) =1) then (PC  PC + 1)
SZA If(AC = 0) then (PC  PC + 1)
SZE rB3:
If(E=0) then (PC  PC + 1)
HLT rB2: S0
rB1:
Input-Output rB0: (Common to all input-output instructions)
(i = 6,7,8,9,10,11)
D7IT3 = p SC  0
INP IR(i) = Bi AC(0-7)  INPR, FGI  0
OUT p: OUTR  AC(0-7), FGO  0
SKI pB11: If(FGI=1) then (PC  PC + 1)
SKO If(FGO=1) then (PC  PC + 1)
ION pB10:
IEN  1
IOF pB9: IEN  0
pB8:
pB7:
pB6:
Computer Organization Computer Architectures Lab
Basic Computer Organization & Design 44

Microprogrammed Control(Control Unit)

Two major types of Control Unit
» Hardwired Control :
The control logic is implemented with gates, F/Fs, decoders, and other digital circuits
Fast operation, - Wiring change(if the design has to be modified) is difficult.
fixed instructions(RISC)
»
» Microprogrammed Control :
The control information is stored in a control memory, and the control memory is programmed to
initiate the required sequence of microoperations for an instruction
 Any required change can be done by updating the microprogram in control memory,
-Slow operation
Variable instructions(CISC)
Control Memory
 Control Unit Initiate sequences of microoperations at given time & disable others
and memory that is a part of control unit is called control memory.
Control Word:In this, the control variables at any given time can be represented
by a string of 1’s and 0’s is called control word.
Control word is programmed to perform different operations on computer.
Microprogrammed Control Unit
A control unit whose binary control variables are stored in memory (control memory)
is called microprogrammed control unit.Every word in a control memory contains
microinstructions.

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 45

 Microinstruction : (Control Word in Control Memory)

• microinstruction specifies one or more microoperations
  Microprogram
• Microprogram is a sequence of microinstruction just like as program is a sequence of
program. It is two type as follow:
• » Dynamic microprogramming : (Control Memory = RAM)
• RAM can be used for writing (to change a writable control memory)
• Microprogram is loaded initially from an auxiliary memory such as a magnetic disk
• » Static microprogramming : (Control Memory = ROM)
• Control words in ROM are made permanent during the hardware production.

User Program

Machine Instruction

Microprogram

Microinstruction

Microoperation
Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 46

Micro programmed Control Organiz

ation
Microprogrammed control Organization :( Fig.(next slide see)
1)Control Memory:memory that is part of control unit is called control
memory.
 Computer that employs a micro programmed control unit will have
two separate memory:::::::::::::::::::::::::
i)Main Memory : for storing user program (Machine instruction/data).
(able to alter) RAM
ii)Control Memory : for storing micro program (Microinstruction)-
(cant altered by user)-ROM-permanently stored
2)Control Address Register:
» Specify the address of the microinstruction..i.e., Sequencer (=
Next Address Generator)
» Determine the address sequence that is read from control memory
» Next address of the next microinstruction can be specified several
way depending on the sequencer input

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 47

Block Diagram of Microprogarmmed Control Me

mory
3) Control Data Register (= Pipeline Register )
» Hold the microinstruction read from control memory
» Allows the execution of the microoperations specified by the control
word
simultaneously with the generation of the next microinstruction
Example(RISC Architecture Concept)

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 48

Address Sequencing
2. Address Sequencing
Address Sequencing = Sequencer : Next Address Generator Selection of
address for control memory
Routine Subroutine : program used by other ROUTINES
Microinstruction are stored in control memory in groups With each group
specify a routine.
each computer instruction has it’s own micro program routine in
control memory to generate microinstructions to execute an instruction.
Mapping : mapping of Instruction Code into Address in control
memorywhere routine is located is called mapping process
Process of Address Sequencing :
1) Incrementing of the control address register
2) Unconditional branch or conditional branch, depending on status bit
conditions
3) Mapping process ( mapping of instruction code to microinstruction
address)
4) A facility for subroutine call and return

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 49 Sequencing
MICROPROGRAM SEQUENCER(SELECTION OF ADDRESS FROM CONTROL MEMORY)

Instruction code

Mapping
logic

Status Branch MUX Multiplexers

bits logic select

Subroutine
register
Control address register (SBR)
(CAR)

Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Storage(procedure for address

sequencing)
- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control
memory
- A Organization
Computer facility for subroutine call and return Computer Architectures Lab
Basic Computer Organization & Design 50

Conditional Branching
Status Bits
» Control the conditional branch decisions generated in the Branch Log
ic
» TestLogic
Branch the specified condition and Branch to the indicated address if the
condition is met ; otherwise, the control address register is just
incremented.

Opcode
Mapping of Instruction :
Computer Instructio 1 0 1 1 Address
n
Mapping bits 0 x xxx 00

Microinstruction Addres 0 1 0 1 1 0 0
s
4 bit Opcode = specify up to 16 distinct instruction
Mapping Process : Converts the 4-bit Opcode to a 7-bit control memory address
» 1) Place a “0” in the most significant bit of the address
» 2) Transfer 4-bit Operation code bits
» 3) Clear the two least significant bits of the CAR (Microinstruction )
Mapping Function : Implemented by Mapping ROM or PLD
Computer
Control
Computer Organization
Memory
System Ar Size : 128 words
Chap. 7(= 27)
Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 51

Subroutine
Subroutines are programs that are used by other routines
» Subroutine can be called from any point within the main body
of the microprogram
Microinstructions can be saved by subroutines that use
common section of microcode
Memory Reference ,Operands Effective Address Subroutine
must have a provision for
» storing the return address during a subroutine call

» restoring the address during a subroutine return Last-In First

Out(LIFO) Register Stack

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 52

Instruction Format
Instruction Format :
» I : 1 bit for indirect addressing

» Opcode : 4 bit operation code

» Address : 11 bit address for system
memory

 Microinstruction Format
:

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 53

Microinstruction format

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 54 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol

000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 55 Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 56

Micro-instruction Types

Micro instruction are two type:

1)vertical micro-programming
2)horizontal micro-programming

vertical micro-programming
Each micro- instruction specifies single (or
few) micro- operations to be performed
horizontal micro-programming
Each micro- instruction specifies many
different micro- operations to be
performed in parallel

56
Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer Architectures
Dept. of Info. Of Compute Lab
Basic Computer Organization & Design 57
Horizontal & vertical microprogramming

Horizontal Micro-
Vertical Micro-programming programming

• Memory Width is narrow • Wide memory word

• n control signals • High degree of
encoded into log2 n bits parallel operations
• Limited ability to express possible
parallelism • Little encoding of
• Considerable encoding control information
of control information • No external decoder
requires external operation is required.
memory word decoder to
identify the exact control
line being manipulated

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 58

Typical Microinstruction Formats

Decoders are there

(only one output will be decoded)

Computer Organization Computer Architectures Lab

Basic Computer Organization & Design 59

QUESTION

Computer
Computer SystemOrganization
Architecture CChhaapp.. 77 MiMiccrroopprrComputer Architectures
ooggrraammmmeedd te Lab
Basic Computer Organization & Design 60

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab
Basic Computer Organization & Design 61

Computer
Computer Organization
System Ar Chap. 7 Microprogrammed Control Computer
Dept. ofArchitectures
Info. Of Comput Lab