MOSFET

(Metal Oxide Field Effect Transistors)

DR UDAI P SINGH
School of Electronics Engineering
[email protected]
Course Coverage

• Basics of MOSFET,
• Two terminal MOS structure and its operation under external bias
condition, Threshold voltage of MOS,
• Qualitative description of MOSFET operation, I-V characteristics of
MOSFET,
• MOSFET as circuit element (CMOS Inverter operation and DC
characteristics, qualitative only),
• High voltage MOSFET and Gallium Nitride power HEMT
(structure and operation),
• III-V high electron mobility transistors, and Multigate MOSFET.
A perspective view of an MOS The cross section of the device
capacitor

We use the convention that the voltage V is positive when the metal plate is positively biased with
respect to the ohmic contact and V is negative when the metal plate is negatively biased with respect
to the ohmic contact.
The energy band diagram of an ideal p-type  The work function is the energy
semiconductor MOS at V = 0
difference between the Fermi level
and the vacuum level (i.e., qϕm for
the metal and qϕs for the
semiconductor)
 the electron affinity q, which is
the energy difference between
the conduction band edge and
the vacuum level in the
semiconductor
qi, the oxide electron affinity,
 qϕB, the energy barrier between the
metal and the oxide
 qψB, the energy difference between
the Fermi level EF and the intrinsic
Fermi level Ei.
Ideal MOS
An ideal MOS is defined as follows: (a) At zero applied bias, the energy
difference between the metal work function qϕm and the semiconductor
work function qϕs is zero, or the work function difference qϕms is zero

(
= = q- qc + + qB ) = 0 ------ (1)
or the energy band is flat (flat-band condition) when there is no applied
voltage.
The only charges that exist in the capacitor under any
biasing conditions are those in the semiconductor and those
with equal but opposite sign on the metal surface adjacent
to the oxide.
• There is no carrier transport through the oxide under direct
current (dc)-biasing conditions, or the resistivity of the oxide
is infinite.
BASICS OF MOSFET
1. Enhancement Type- Normally OFF

p-channel MOSFET p-channel MOSFET

But generally displayed as
 n-channel MOSFET n-channel MOSFET
The enhancement-type MOSFET operates only in the enhancement mode.
 Figure shows an n-channel enhancement-mode
MOSFET with the source and substrate terminals
connected to the zero. When the Gate to source
voltage is less than the threshold voltage, there is no
current flow from the channel, it’s called a cut-off
region. The drain current is zero(we are neglecting PN
junction leakage current)

Now if we increase the gate voltage, Figure shows

the same MOSFET with an applied gate voltage
greater than the threshold voltage. In this
situation, an inversion layer (acceptor ions) is
created, and, when a small drain voltage is
applied, electrons in the inversion layer flow from
the
source to the drain terminal.
Acceptor ions
2. Depletion Type- Normally ON

You can try p-channel MOS !!

• The conduction channel is physically implanted
• If the value of VGS is positive, the channel is further enhanced. That is
more free electrons are attracted to the channel, and its conductivity
increases.
• If the value of VGS is negative, free electrons are repelled from the
channel. The conductivity of the channel is thus decreased  channel
depletion.
• If the value of VGS becomes sufficiently negative most of the electrons in
the channel will be repelled the channel is said to be completely
depleted.
• A channel that is completely depleted cannot conduct. In other words,
the depletion MOSFET is in cut-off.
• Thus, the negative value of VGS at which the channel is completely
depleted is the threshold voltage VT for a depleted N-MOS device.
• In other words, to have a conducting channel, the gate to source voltage
• The threshold voltage for a depletion NMOS device is negative ( i.e.
VT<0)
• While the threshold voltage for a depletion PMOS device is positive
(i.e. VT>0)
Symbols
Enhancement Type Depletion Type MOSFET

Replace the broken line by continuous line

When an ideal MOS
diode is biased with
positive or negative
voltages, basically
three cases may
exist at the
semiconductor
surfaces
More holes accumulate at the surface of
the
semiconductor.
+ve
• Deposition of positive charge on the gate requires
compensation by negative charges in the
semiconductor.
• The negative charge in a p-type semiconductor arises
from the depletion of holes from the surface.
• This leaves behind uncompensated ionized
acceptors.
• The bands bend downward near the semiconductor
surface (EI closer to EF).
• What happens if we keep increasing the amount of
positive gate voltage we apply to the metal relative to
the semiconductor?
 ∅𝑠 ∅𝑓

=
= surface potential (Ei bulk- Ei surface) = Fermi potential (Ei-Ef)
We assume uniformly doped semiconductor. Under these assumptions the
electron and hole concentration at any point in semiconductor are given by
= =
The hole concentration in the bulk of p-type substrate
= where Eib is intrinsic fermi level in neutral (bulk)
semiconductor
We define Fermi potential by the relation = -), so
=
When all acceptors are ionized, = NA, then from(2) we can write
Similarly hole concentration at the surface
= where -> the intrinsic fermi level at the
surface
Now from (1) and (4) =
The surface potential (= q , so
= and =
We have seen that Fermi Potential is
ln ----- (p-type )

ln ----- (n-type )
For a p-type semiconductor the onset of inversion is given by the
condition
Inversion takes place when >
• Strong inversion is said to occur when minority carrier
concentration at the surface becomes equal to the majority carrier
concentration in the bulk.
• For a p-type semiconductor this means that ns = po and the surface
potential for this condition i.e.
for strong inversion =2
We know the space charge width for (p+n) one sided junction
1/2 1/2
W= or

1/2
And for strong inversion  (a)
(for strong inversion = )

(we know ln ) ----- (p-type )

The charge per unit area in the depletion region Qd at strong inversion
=W, using the value of W from (a) we can write
= )1/2
Flat Band Voltage: The flat band voltage is defined as the applied gate
voltage such that there is no band bending in the semiconductor
(Because of the work function difference and possible trapped charges
in the oxide, the voltage across oxide for this case is not necessarily
zero)
Threshold Voltage:
• The point in the gate voltage sweep when significant current begins to
flow is the threshold voltage, VT.
• This corresponds to the point when the channel is formed under the
gate.
• The onset of inversion occurs for a voltage called the threshold
voltage VT
• An applied voltage V appears across the insulator/oxide (Vi) and partially
across the depletion region of the semiconductor.

• The voltage across the insulator is related to the charge on either side,
divided by the capacitance
=
Where is permittivity of insulator and is the insulator capacitance per unit area
The charge will be negative for the n-channel giving a positive .
• For the strong inversion, the applied voltage must be large enough to
create the depletion charge = )1/2 ) plus the surface potential (inv.)
• The threshold voltage required for strong inversion
= - (ideal case)
• This assumes the negative charge at the semiconductor surface at
inversion is mostly due to the depletion charge
• The threshold voltage represents the minimum voltage required to achieve
strong inversion.
• When MOS devices are made using typical materials (e.g., metal-high
k/SiO2-Si), departures from the ideal case strongly affect the VT and other
properties.
• First, there is a work function difference between the metal gate and
substrate/semiconductor, which depends on the substrate doping.
(Initially we have assumed =)
• Second, there are inevitably charges at the Si-high-k/SiO2 interface and within the
oxide which must be taken into account.
• To obtain the flat band condition, one must apply a negative voltage to the
metal (for p-type semiconductor)
• In addition to the work function difference, the equilibrium MOS structure
is affected by charges in the insulators and at the semiconductor-oxide
interface.
• Finally the flat band voltage
• The voltage required to achieve flat band should be added to the
threshold voltage equation = - (ideal case)
• The threshold voltage is given as
=-

 the threshold voltage depends on the following:

1) the work function difference between the Gate and the Channel
2) the gate voltage necessary to change the surface potential
3) the gate voltage component to offset the depletion region charge
4) the gate voltage necessary to offset the fixed charges in the Gate-Oxide and Si-
Oxide junction
MOS Capacitance
• An incremental change in the applied voltage () causes a corresponding
change in the density of the accumulation charge ()
• This situation is equivalent to an ordinary metal-dielectric-metal
capacitor.
• Therefore, the capacitance per unit area in the accumulation mode is
determined by the gate oxide thickness

= (prime denotes “per unit area”)

• As the gate voltage is increased and made positive, holes are
driven away from the semiconductor interface and a depletion
region develops in the semiconductor sur­face.
• This region is made up of negatively charged acceptor atoms.
• The capacitance in the depletion mode is the series
combination i) oxide capacitance and ii) capacitance of the
depletion region.
= or or =
We know, and , so the above equation can be written as

As the surface charge or depletion width increases, the total

depletion capacitance decreases
• The threshold inversion point is defined as the condition when the
maximum depletion width is reached but there is essentially zero
inversion charge density.
• This condition will yield a minimum capacitance

, where is the maximum depletion width

• For the case of inversion, in the ideal case a small incremental change in
the voltage across the MOS capacitor will cause a differential change in
the inversion layer charge density.
• The space charge width does not change
• If the inversion charge can respond to the change in capacitor voltage,
=
 Strong Inversion
n
ve rsio
I n
te
d era
Mo

o n
eti
pl
De
Strong Inversion
(Deep depletion)
 MOSFET I-V Characteristics
• we have seen how the Gate-to-Source voltage (VGS) induces a channel
between the Source and Drain for current to flow through
• this current is denoted IDS - remember that this current doesn't flow unless a
potential exists between VD and VS
• the voltage that controls the current flow is denoted as VDS
• once again, we start by applying a small voltage and watching how I DS
responds
• notice that now we actually have two control variables that effect the current
flow, VGS and VDS
• this is typical operating behavior for a 3-terminal device or transistor
• we can use an enhancement n-channel MOSFET to understand the IV
characteristics
Linear Region (cont.)
• when a voltage is applied at VD, its positive charge pushes the majority charge carriers
(holes) that exist at the edge of the depletion region further from the Drain.
• as the depletion region increases, it becomes more difficult for the Gate voltage to induce
an inversion layer. This results in the inversion layer depth decreasing near the drain.
• as VD increases further, it eventually causes the inversion layer to be pinched-off and
prevents the current flow to increase any further.
• this point is defined as the saturation voltage (VDSAT)
• from this, we can define the linear region as:
VGS>VT
0 < VDS < VDSAT
Saturation Region
• a MOSFET is defined as being in saturation when:
VGS > VT
VDS > (VGS-VT)
• an increase in VDS does not increase IDS because the channel is pinched-
off
• However, an increase in VGS DOES increase IDS by increasing the channel
depth and hence the amount of current that can be conducted.
• measurements on MOSFETS have shown that the dependence of IDS on
VGS tends to remain approximately constant around the peak value
reached for VDS=VDSAT
Till slide 41 is the course for Mid Semester
 D VDD D
PMOS
(p-channel MOS)
G
I/P SS (Substrate)
O/P G
S
D D S

The broken line in the symbol indicates that

there is no conducting channel between
these electrodes
VGS (-ve) 1K VGS (+ve) 1010

S S
ON OFF
NMOS (n-channel MOS)
D D
VDD
D
O/P

VGS(+ve) 1K VGS(-ve) 1010

G
S

S S
D
ON OFF

SS (Substrate)
G
S
CMOS as Inverter
VDD PMOS If input =0, S to D  short circuit
If input =1, S to D  open circuit
S
NMOS If input =0, S to D  open circuit
If input =1, S to D  short circuit
PMOS Q1

D
O/P
Vin Vo
G D
I/P
Vin Q1 Q2 VO
NMOS Q2 PMOS NMOS
S O ON OFF 1
1 OFF ON 0