DCIT 416

DIGITAL SIGNAL PROCESSING

Session 6– DIGITAL SIGNAL PROCESSOR

Mareh Williams – 10867053

Emmanuel Kodjo Djangmah - 10868218

College of Education
School of Continuing and Distance Education
2017/2018 – 2018/2019 ACADEMIC YEAR
 Session Outline

 Digital Signal Processor Architecture

 Digital Signal Processor Hardware Units
 Fixed & Floating Point Format
 Fixed & Floating Point Digital Signal Processor

Slide 2
Topic One
DIGITAL SIGNAL
PROCESSOR ARCHITECTURE

Slide 3
 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Digital Signal Processor Architecture refers to the
architecture designed to develop a processor that
efficiently handles the computation of digital signal
processing tasks.

 Processors can be designed to follow two forms of

architecture; the Von Neuman Architecture built for
microprocessors and the Harvard Architecture built for
digital signal processors.

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 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Von Neumann Architecture(Microprocessors)
Von Neumann suggested that computer instructions should be in
numerical code instead of special wiring.
It consists of:
i. a shared memory for programs and data.
ii. a single bus for memory and arithmetic unit.
iii. a program control unit.

 The von Neumann architecture follows a serial fashion where the CPU
fetches an instruction from memory, decodes it to identify the operation,
and then executes it. Each instruction is divided into an opcode and an
operand; the opcode specifies the operation to be performed, while the
operand specifies the data to be operated on.
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 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Von Neumann Architecture

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 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Von Neumann Architecture
Execution cycle based on Von Neumann Architecture

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 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Von Neumann Architecture
While simple and flexible, this architecture can be
limited by the von Neumann bottleneck, where the
shared memory slows down processing because
instructions and data cannot be accessed
simultaneously.

1-8
 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Harvard Architecture
This architecture differs from the previous by having two
separate spaces in memory for programs and data
resulting in two corresponding buses for each, allowing
simultaneous access to both. While it introduces
complexity and higher costs due to the need for distinct
memory and bus systems, the improved efficiency and
speed make it advantageous for tasks requiring frequent
and rapid memory access.

1-9
 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Harvard Architecture

1-10
 DIGITAL SIGNAL PROCESSOR
ACHITECTURE
 Harvard Architecture
Execution cycle based on the Harvard Architecture

1-11
Topic One
DIGITAL SIGNAL PROCESSOR
HARDWARE UNITS

Slide 12
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 DSPors hardware units are specialized components
designed to efficiently execute digital signal processing
tasks. These units are optimized for high-speed
numerical calculations and real-time processing.
 These hardware include:
a. Multiplier & Accumulator (MAC)
b. Address Generator
c. Shifters

1-13
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Multiplier & Accumulator (MAC)
The MAC unit is a crucial component in DSP hardware, designed to
perform high-speed arithmetic operations that are fundamental to
many DSP algorithms. MAC stands for Multiply-Accumulate.
 The MAC unit performs two main operations in a single cycle:
Multiplication and Accumulation. The unit works by taking two
input values, multiplies them and combines it to the current value
of the accumulator. This process is repeated for each pair of input
values, updating the accumulator with each cycle.
 The MAC operation is central to many DSP tasks because it
efficiently handles the repetitive multiplications and additions
required in filtering, convolution and Fast Fourier Transform (FFT).
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 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Multiplier & Accumulator (MAC)

1-15
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Shifters
Shifters in DSPors are specialized hardware units
designed to perform rapid shifting operations on binary
data. These operations are fundamental in various DSP
tasks, such as scaling, bit manipulation, and arithmetic
operations.
 Types of Shifters:
Logical Shifters
Arithmetic Shifters
Circular (or Rotational) Shifters
1-16
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Logical Shifters are instructions in a processor that
perform bitwise shifting operations on binary numbers.
There exists 2 types:
 Logical Left Shift (LLS): Shifts bits to the left, filling the
vacant least significant bit (LSB) positions with zeros.
Example: Shifting 0010 left by 1 bit results in 0100.
 Logical Right Shift (LRS): Shifts bits to the right, filling
the vacant most significant bit (MSB) positions with
zeros. Example: Shifting 0100 right by 1 bit results in
0010.
1-17
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Arithmetic Shifters are instructions in a processor that
perform bitwise shifting operations on binary numbers
particularly useful for signed integers. There exists 2 types:
 Arithmetic Left Shift (ALS): Like LLS, shifts bits to the left
and fills the LSB positions with zeros. Example: Shifting
0010 left by 1 bit results in 0100.
 Arithmetic Right Shift (ARS): Shifts bits to the right,
preserving the sign bit (MSB) for signed numbers. Example:
Shifting 1100 (binary for -4 in two's complement) right by 1
bit results in 1110 (binary for -2 in two's complement).

1-18
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Address Generator
An address generator is a hardware unit responsible for
generating addresses for each data on the data buffer to
be processed efficiently. The DSPor will generate an
address for each data on the data buffer to be
processed. This is used with circular buffering to
efficiently manage and access memory in DSPors.

1-19
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Circular buffering is a method of managing a fixed-size
buffer that allows for continuous writing and reading of
data in a circular manner. When the end of the buffer is
reached, the operations wrap around to the beginning,
creating a loop.
 The circular buffer provides a continuous stream of
data, while the address generator ensures that the DSP
processor accesses the correct memory locations in the
required sequence.

1-20
 DIGITAL SIGNAL PROCESSOR HARDWARE
UNITS
 Imagine a circular buffer with 5 slots: [_, _, _, _, _]
- Write data: Add 1, buffer becomes [1, _, _, _, _]
- Add 2, buffer becomes [1, 2, _, _, _]
- Add 3, buffer becomes [1, 2, 3, _, _]
- Add 4, buffer becomes [1, 2, 3, 4, _]
- Add 5, buffer becomes [1, 2, 3, 4, 5]

Now it’s full. To add more data, you need to read some first.
Read one item (1): The buffer becomes [_, 2, 3, 4, 5]
Add new data (6): The buffer becomes [6, 2, 3, 4, 5]

 An address generator would automate the calculation of the next read

and write addresses, ensuring the operations wrap around correctly.
1-21
Topic One
FIXED POINT FORMAT

Slide 22
 FIXED-POINT FORMATS
 Depending on how the CU performs arithmetic in a
DSPor we have two formats for representing fractional
numbers, firstly, Fixed-Point Format and secondly,
Floating-Point Format.
 Fixed-Point Format is a way of representing fractional
numbers in digital systems, where the number is
represented by an integer along with a fixed position for
the binary point. Example of this is the 3-bit Two's
Complement Representation and Q-format number
representation.
1-23
 FIXED-POINT FORMATS
 The 3-bit Two's Complement Representation is a method for
representing signed integers in binary. In a 3-bit system, the
range of representable integers is from -4 to +3.
 Decimal number 2’s complement
3  011
2  010
1  001
0  000
-1  111
-2  110
-3  101
-4  100
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 FIXED-POINT FORMATS
 The rules in converting a decimal to a 3 bit 2’s
complement are:
a. If the number is positive, the binary number is its 2s
complement representation.
b. If the number is negative, find the 2s complement
operation, negate 0 to 1 and 1 to 0. After such, add 1 to
the data.

1-25
 FIXED-POINT FORMATS
 Example:
a. 3 in 3 bits 2s complement representation is 011

b. -3  011 = 100+1 = 101

c. 2 -1
= 2 1 = 010 001 = 00010 = 11101 + 1 = 11110
Since its 3 bit 2s complement we must get rid of the first
2 bits of the result resulting in 110 = -2

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 FIXED-POINT FORMATS
 Decimal number Decimal fraction 2s complement
3 3/4 0.11
2 2/4 0.10
1 1/4 0.01
0 0 0.00
-1 -1/4 1.11
-2 -2/4 1.10
-3 -3/4 1.01
-4 -4/4 = 1 1.00

3bit 2s complement using fractional representation

1-27
 FIXED-POINT FORMATS
 Example:2 -3
Ans:
0.10 0.11 = 0.0110
=(after 2s complement) 1.1001 +1 = 1.1010

Converting back to decimal:

1.1010 = (-1)(0.0110)
=
= -3/8
= 2/4 -3/4 = -3/8

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 FIXED-POINT FORMATS
 Q-Format Number Representation (Q-15 format)
The Q15 format is a specific type of fixed-point number
representation where 16 bits are used to represent a
number, with 1 bit for the integer part (sign bit) and 15
bits for the fractional part.

1-29
 FIXED-POINT FORMATS
• Example: Represent 0.560123 in Q15 format
Solution
0.560123 2 = 1.120246 1[MSB]
0.120246 2 = 0.240492 0
0.240492 2 = 0.480984 0
0.480984 2 = 0.961968 0
0.961968 2 = 1.923936 1
0.923936 2 = 1.847872 1
0.847872 2 = 1.695744 1
0.695744 2 = 1.391488 1
0.391488 2 = 0.782976 0
0.782976 2 = 1.565952 1
0.565952 2 = 1.131904 1
0.131904 2 = 0.263808 0
0.263808 2 = 0.527616 0
0.527616 2 = 1.055232 1
0.055232 2 = 0.110464 0[LSB]
Slide 30
 FIXED-POINT FORMATS
• Example: Represent 0.560123 in Q15 format
Solution
Therefore 0.560123 = 0.10011110110010 in Q15
format.
You’ll find out that the binary of (0.560123) = 18354
is 0.10011110110010

Slide 31
 FIXED-POINT FORMATS
• Example: Represent -0.560123 in Q15 format
Solution
First find 0.560123 in Q15 format which is
0.10011110110010.
Now performing 2s complement =
1.01100001001101 + 1 = 1.001100001001110
Therefore -0.560123 in Q15 format is
1.001100001001110

Slide 32
Topic One
FLOATING POINT FORMAT

Slide 33
 FLOATING POINT FORMAT
 Floating-point format is a method used to represent
real numbers (both rational and irrational) in
computers, allowing them to increase the dynamic
range of number representation. It consists of two
main components: a significand (or mantissa) and an
exponent.
 The equation is given by , where M represents the
mantissa or fractional part in Q-format and E
represents the exponent. M and E are always signed
numbers.
Slide 34
 FLOATING POINT FORMAT
 In the floating-point format, the first 4 bits of the number
represents the exponent and the last 12 bit represent the mantissa.
 The mantissa ranges between -1 and +1.

 The dynamic range is controlled by the number of bits assigned to

the exponent side of the number.
 The interval in the normalized range is defined by the number of
bits in the mantissa.

Slide 35
 FLOATING POINT FORMAT
 Example: 0.1601230
Solution
Expanding 0.1601230 = 0.640492
2s comp. of -2 = 1110
Q11 format of 0.640492 = 010100011111
Combining it produces 1110010100011111

Slide 36
Topic One
IEEE FLOATING POINT
FORMAT
Slide 37
 IEEE FLOATING POINT FORMAT
 The IEEE floating point format defines formats for
representing floating-point numbers and specifies
operations on them. The two most common formats
defined by IEEE are single precision (32-bit) and
double precision (64-bit).

Slide 38
 IEEE FLOATING POINT FORMAT
 Single precision format, also referred to as single-
precision floating-point format, uses 32 bits to
represent a wide range of real numbers.
 Single Precision Format Floating Point standard
representation requires 23 fraction bits, 8
exponential bits and 1 sign bit. Fraction bit is
represented as F, exponent as E and sign bit as S.

Slide 39
 IEEE FLOATING POINT FORMAT
 The standard representation of single precision
format is given by
 F represents mantissa in 2’s comp binary fraction and
it ranges from +1 to +2
 Sign=0  number is positive
Sign=1  number is negative
 The 8 bit exponent is in Excess 127 form and it ranges
from 0 to 255
 E-127 ranges from -127 to 128

Slide 40
 IEEE FLOATING POINT FORMAT
 Double precision format, often referred to as
double-precision floating-point format, is a computer
number format that uses 64 bits to represent a wide
range of real numbers.
 Double Precision Format Floating Point standard
represents 1 sign bit, exponent bit and the final 52
bit are the fraction bit

Slide 41
 IEEE FLOATING POINT FORMAT
 Double precision significantly increases the dynamic
range of the number representation and reduces the
interval size of the mantissa since there are 52
mantissa bits.
 To convert into double precision format the following
equation can be used

Slide 42
Topic One
FIXED POINT DIGITAL
SIGNAL PROCESSOR
Slide 43
 FIXED POINT DIGITAL SIGNAL
PROCESSOR
 A fixed-point digital signal processor (DSP) is a
specialized microprocessor designed for high-speed
numerical computations typically used in real-time
signal processing applications. An example of this
type of processor is the TMS320C54x Family.
 The TMS320C54x family uses a six-stage pipeline
(Fetch, Decode, Address, Read, Execute, Write),
allowing multiple instructions to be processed
simultaneously, which improves throughput and
efficiency.
Slide 44
Topic One
FLOATING POINT DIGITAL
SIGNAL PROCESSOR
Slide 45
 FIXED POINT DIGITAL SIGNAL
PROCESSOR
 Floating-point digital signal processors are powerful
microprocessors designed for applications requiring high precision
and a wide dynamic range.
 Floating-point DSPs often have multiple pipeline stages dedicated to
different phases of the floating-point arithmetic operation, such as
operand fetch, execution, and result write-back.
 It supports three types of floating-point formats:
- 16 bit floating point format that has, 4 exponent bit, one sign bit
and 11 mantissa bits
- 32 bit single precision format, 8 exponent bit, one sign bit and 23
mantissa bit.
- 40 bit precision format, 8 exponent bit, one sign bit and 31
mantissa bit.
Slide 46
 The End

College of Education
School of Continuing and Distance Education
2017/2018 – 2018/2019 ACADEMIC YEAR