COMPUTER ORGANISATION

AND ARCHITECTURE

NAAC A+

GAURAV GUPTA
Computer Science & Engineering
TULA’S INSTITUTE DEHRADOON
WINTER-2024
 Computer Organization and
Architecture
Computer Organization and Architecture is used to
design
computer systems.
Computer Architecture is considered to be those
attributes of a system that are visible to the user like
addressing techniques, instruction sets, and bits used for
data, and have a direct impact on the logic execution of a
program, It defines the system in an abstract manner, It
deals with What does the system do.
Whereas, Computer Organization is the way in which a
system has to structure and It is operational units and the
interconnections between them that achieve the
architectural specifications, It is the realization of the
abstract model, and It deals with How to implement the
system.
Lecture #00: © GAURAV
CST-007 : COMPUTER ORGANISATION & 2
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Different ways to represent Signed Integer
A signed integer is an integer with a positive ‘+’ or negative sign ‘-‘ associated with it. Since the computer
only understands binary, it is necessary to represent these signed integers in binary form.
In binary, signed Integer can be represented in three ways:
1.Signed bit.
2.1’s Complement.
3.2’s Complement.
Signed bit Representation
In the signed integer representation method the following rules are followed:
1. The MSB (Most Significant Bit) represents the sign of the Integer.
2. Magnitude is represented by other bits other than MSB i.e. (n-1) bits where n is the no. of bits.
3. If the number is positive, MSB is 0 else 1.
4. The range of signed integer representation of an n-bit number is given as –(2^{n-1}-1) to (2)^{n-1}-1.
Let n = 4
Range:
–(2^{4-1}-1) to 2^{4-1}-1
= -(2^{3}-1) to 2^{3}-1
= -(7) to+7
For 4 bit representation, minimum value=-7 and maximum value=+7

1’s Complement representation of a signed integer

In 1’s complement representation the following rules are used:
1. For +ve numbers the representation rules are the same as signed integer representation.
2. For –ve numbers, we can follow any one of the two approaches:
•Write the +ve number in binary and take 1’s complement of it.
1’s complement of 0 = 1 and 1’s complement of 1 = 0
Example:
(-5) in 1’s complement:
+5 = 0101
-5 = 1010
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Different ways to represent Signed Integer
2’s Complement representation

In 2’s Complement representation the following rules are used:

1. For +ve numbers, the representation rules are the same as signed integer representation.
2. For –ve numbers, there are two different ways we can represent the number.
•Write an unsigned representation of 2^n-X for –X in n-bit representation.

Example:
(-5) in 4-bit representation
2^4-5=11 -→1011(unsigned)

To take 2’s complement simply take 1’s complement and add 1 to it.
Example:
(-5) in 2’s complement
(+5) = 0101
1’s complement of (+5) = 1010
Add 1 in 1010: 1010+1 = 1011
Therefore (-5) = 1011

3. Range of representation of n-bit is –(2^{n-1} ) to (2)^{(n-1)-1}.

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Fixed Point Representation

Real numbers have a fractional component. This article explains the real number representation
method using fixed points. In digital signal processing (DSP) and gaming applications, where
performance is usually more important than precision, fixed point data encoding is extensively used.

The Binary Point: Fractional values such as 26.5 are represented using the binary point concept. The
decimal point in a decimal numeral system and a binary point are comparable. It serves as a divider
between a number’s integer and fractional parts.
For instance, the weight of the coefficient 6 in the number 26.5 is 10 0, or 1. The weight of the
coefficient 5 is 10-1 or (5/10 = 1/2 = 0.5).
2 * 101 + 6 * 100 + 5 * 10-1 = 26.5

A “binary point” can be created using our binary representation and the same decimal point concept.
A binary point, like in the decimal system, represents the coefficient of the expression 2 0 = 1. The
weight of each digit (or bit) to the left of the binary point is 2 0, 21, 22, and so forth. The binary point’s
rightmost digits (or bits) have weights of 2 -1, 2-2, 2-3, and so on.

For illustration, the number 11010.12 represents the value:

11010.12
= 1 * 24 + 1 * 23 + 0 * 22 + 1 * 21 + 0* 20 + 1 * 2-1
= 16 + 8 + 2 + 0.5
= 26.5
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Fixed Point Representation

Shifting Pattern:
When an integer is shifted right by one bit in a binary system, it is comparable to being
divided by two. Since we cannot represent a digit to the right of a binary point in the case of
integers since there is no fractional portion, this shifting operation is an integer division.
•A number is always divided by two when the bit pattern of the number is shifted to the right
by one bit.
•A number is multiplied by two when it is moved left one bit.
How to write Fixed Point Number?
Understanding fixed point number representation requires knowledge of the shifting process
described above. Simply by implicitly establishing the binary point to be at a specific place
of a numeral, we can define a fixed point number type to represent a real number in
computers (or any hardware, in general). Then we will just use this implicit standard to
express numbers.
Two arguments are all that are required to theoretically create a fixed point type:
1.Width of the number representation.
2.Binary point position within the number.
the notation fixed<w, b>, where “w” stands for the overall amount of bits used (the width of
a number) and “b” stands for the location of the binary point counting from the least
significant bit (counting from 0).
Unsigned representation:
For example, fixed<8,3> signifies an 8-bit fixed-point number, the rightmost 3 bits of which
are fractional.
Representation of a real number:
00010.1102
= 1 * 21 + 1 * 2-1 + 1 * 2-2
=CST-007:
2 + 0.5COMPUTER
+ 0.25 ORGANISATION Lecture #00: © GAURAV
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Fixed Point Representation

Shifting Pattern:
When an integer is shifted right by one bit in a binary system, it is comparable to being
divided by two. Since we cannot represent a digit to the right of a binary point in the case of
integers since there is no fractional portion, this shifting operation is an integer division.
•A number is always divided by two when the bit pattern of the number is shifted to the right
by one bit.
•A number is multiplied by two when it is moved left one bit.
How to write Fixed Point Number?
Understanding fixed point number representation requires knowledge of the shifting process
described above. Simply by implicitly establishing the binary point to be at a specific place
of a numeral, we can define a fixed point number type to represent a real number in
computers (or any hardware, in general). Then we will just use this implicit standard to
express numbers.
Two arguments are all that are required to theoretically create a fixed point type:
1.Width of the number representation.
2.Binary point position within the number.
the notation fixed<w, b>, where “w” stands for the overall amount of bits used (the width of
a number) and “b” stands for the location of the binary point counting from the least
significant bit (counting from 0).
Unsigned representation:
For example, fixed<8,3> signifies an 8-bit fixed-point number, the rightmost 3 bits of which
are fractional.
Representation of a real number:
00010.1102
= 1 * 21 + 1 * 2-1 + 1 * 2-2
=CST-007:
2 + 0.5COMPUTER
+ 0.25 ORGANISATION Lecture #00: © GAURAV
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=AND
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SIGNED MAGNITUDE ADDITION AND SUBTRACTION

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SIGNED MAGNITUDE ADDITION AND SUBTRACTION

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SIGNED MAGNITUDE ADDITION AND SUBTRACTION

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SIGNED MAGNITUDE ADDITION AND SUBTRACTION

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Signed Operand Multiplication Algorithm

HARDWARE REPRESENTATION

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Signed Operand Multiplication Algorithm

FLOW CHART

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Signed Operand Multiplication Algorithm

EXAMPLE

Multiplicand = 10111
Multiplier = 10011

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BOOTH’S MULTIPLICATION PROCESS

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Fixed point Division

On dividing, we obtained 42 as quotient

and 3 as remainder. Observe that:
•The number of bits taken at the first
instance equals that of the bits in the
divisor; these bits are considered from
MSB onwards. In this case, it is 3-bits at
a time.
•This set of bits from the dividend are
compared with divisor. If dividend set is
greater than the divisor, a '1' is placed in
the quotient, else a '0' is placed in
quotient.
•The partial reminder at this stage is
derived by subtraction of the divisor
from the dividend set of bits.
•The next most significant bit from the
divisor is appended to the partial
reminder.
•The divisor is shifted right.
•Steps 2 to 5 are repeated until all the bits
in dividend are used up
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* Restoring Division
In the process of division, at each
step, we need to know whether the
dividend set is higher than the
divisor. This can be done by
subtraction or comparison.
Restoring division is a method
wherein, by default, without
identifying the magnitude of the
dividend set, the divisor is
subtracted. This is called trial
subtraction. If the result of trial
subtraction is positive, then the
quotient is marked '1' and also the
subtraction becomes the desired
step. However, if the trial
subtraction result is negative then
this becomes an undesired step
necessitating a correction; and
hence the step is reverted or
restored by adding the divisor.
Subsequently, the quotient is
marked '0. For this reason, this
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method of division algorithm
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called Restoring Division method.
 * Restoring Division Example

N M A Q Operation
4 00011 00000 1011 Initialize
1.Dividend = 11 00011 00001 011_ Shift left AQ
2.Divisor = 3
00011 11110 011_ A=A-M
00011 00001 0110 Q[0] = 0 And
restore A

3 00011 00010 110_ Shift left AQ

00011 11111 110_ A=A-M
00011 00010 1100 Q[0] = 0
2 00011 00101 100_ Shift left AQ
00011 00010 100_ A=A-M
00011 00010 1001 Q[0] = 1
1 00011 00101 001_ Shift left AQ
00011 00010 001_ A=A-M
00011 00010 0011 Q[0] = 1
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* Non Restoring Division Algo Let’s pick the step involved:
•Step-1: First the registers are
initialized with corresponding
values (Q = Dividend, M = Divisor,
A = 0, n = number of bits in
dividend)
•Step-2: Check the sign bit of
register A
•Step-3: If it is 1 shift left content
of AQ and perform A = A+M,
otherwise shift left AQ and perform
A = A-M (means add 2’s
complement of M to A and store it
to A)
•Step-4: Again the sign bit of
register A
•Step-5: If sign bit is 1 Q[0]
become 0 otherwise Q[0] become
1 (Q[0] means least significant bit
of register Q)
•Step-6: Decrements value of N by
1
•Step-7: If N is not equal to zero
go to Step 2 otherwise go to next
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•Step-8: If sign bit of A is 1 then
* Non Restoring Division Example 1.Dividend (A) = 101110
2. Divisor (M) = 010111

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IEEE 754 Floating Point Representation

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical

standard for floating-point computation which was established in 1985 by
the Institute of Electrical and Electronics Engineers (IEEE). The standard
addressed many problems found in the diverse floating point implementations
that made them difficult to use reliably and reduced their portability. IEEE
Standard 754 floating point is the most common representation today for real
numbers on computers, including Intel-based PC’s, Macs, and most Unix
platforms. There are several ways to represent floating point number but IEEE
754 is the most efficient in most cases. IEEE 754 has 3 basic components:

1.The Sign of Mantissa – This is as simple as the name. 0 represents a positive number
while 1 represents a negative number.
2.The Biased exponent – The exponent field needs to represent both positive and
negative exponents. A bias is added to the actual exponent in order to get the stored
exponent.
3.The Normalised Mantissa – The mantissa is part of a number in scientific notation or
a floating-point number, consisting of its significant digits. Here we have only 2 digits,
i.e. O and 1. So a normalised mantissa is one with only one 1 to the left of the decimal.

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IEEE 754 Floating Point Representation
IEEE 754 numbers are divided into two based on the
above three components: single precision and double
precision.

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 IEEE 754 Floating Point Representation
Example:

85.125 85 = 1010101
0.125 = 001
85.125 = 1010101.001 =1.010101001 x 2^6 sign = 0

1. Single precision: biased exponent 127+6=133 133 = 10000101

Normalised mantisa = 010101001 we will add 0's to complete the 23 bits

The IEEE 754 Single precision is: = 0 10000101 01010100100000000000000

This can be written in hexadecimal form 42AA4000

2. Double precision: biased exponent 1023+6=1029 1029 = 10000000101

Normalised mantisa = 010101001 we will add 0's to complete the 52 bits

The IEEE 754 Double precision is: = 0 10000000101

0101010010000000000000000000000000000000000000000000
This can be written in hexadecimal form 4055480000000000

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 IEEE 754 Floating Point Arthimatic Operations
Example:

Will Discuss in class

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* Execution of Complete Instruction

Purpose of the control Unit is to generate

the control signal to implement
microoperation.

A high level instruction is divided into

multiple machine instruction.

A machine instruction is divided into

microinstruction like(IF,ID,OF,E,S).

A micro instruction further divided into

microoperation, it result actual movement
of data from one register another register.

Microoperations are atomic and ended

with register transfer language(RTL).

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* Execution of Complete Instruction

INSTRUCTION FETCH AND DECODE

1. PC MAR
2. MDR MAR
3. IR MDR, PC PC+ SETP SIZE

FOR 16 BIT INSTRUCTION

3 BIT WILL GIVEN TO 3*8 DECODER
12 BIT(LSB) FOR GIVEN
INFORMTION ABOUT NO OF
OPERANDS AND TYPE OF OPERANDS

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* Execution of Complete Instruction

OPERAND FETCH:

IMMEDIATE AM:

IR[add] ALU

DIRECT AM:
IR[add] MAR MDR ALU

REGISTER AM:
IR[add] R ALU
REGISTER INDIRECT AM:
IR[add] R MAR MDR ALU

INDIRECT AM:

IR[add] MAR MDR MAR

MDR ALU

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* Execution of Complete Instruction

READ OPERATION:

MOV R2, (R1) R2 M[R1]

ACTION NEEDED TO EXECUTE

1. MAR M[R1]
2. Start Read Operation on memory bus
3. Wait for MFC(memory function
complete) response from memory
4. Load MDR from memory Bus
5. R2 MDR

CONTROL SIGNAL

 R1OUT,MARIN, READ
 MDRMIN,WMFC
 MDRPOUT, R2IN

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* Execution of Complete Instruction

WRITE OPERATION:

MOV (R1),R2 M[R1] R2

ACTION NEEDED TO EXECUTE

1. MAR M[R1]
2. Copy the content of R2 in MDR
3. Inform the memory for write operation
4. Wait for WMFC
CONTROL SIGNAL

 R1OUT,MARIN
 MDRMIN,R2OUT, WRITE
 MDRMOUT, WMFC

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* Execution of Complete Instruction

EXECUTION OF COMPLETE
INSTRUCTION

ADD R1, (R3) R1 R1+ M[R3]

ACTION NEEDED TO EXECUTE

1. Fetch the instruction
2. Fetch the first operand(content of memory
location pointed by R3.
3. Perform the addition
4. Load results in R1.
CONTROL SIGNAL
 PCOUT,MARIN,SELECT4,ADD,ZIN,READ
 ZOUT,PCIN,MDRMIN,WMFC
 MDRPOUT,IRIN
 R3OUT,MARIN,READ
 R1OUT, YIN,MDRMIN,WMFC
 MDRPOUT,YOUT,SELECT Y,ADD,ZIN
 ZOUT,R1IN,EXIT

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 Any question?

You may post your question(s) at the “Discussion

Forum” maintained in the course Web page.
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