Computer Organization & Architecture

COA Practice Problems

Dr. SHAKTI KUNDU

JAN-MAY 2025
Amdahl’s law and its proof

 It is named after computer scientist Gene Amdahl( a computer architect from

IBM and Amdahl corporation) and was presented at the AFIPS Spring Joint
Computer Conference in 1967. It is also known as Amdahl’s argument. It is a
formula that gives the theoretical speedup in latency of the execution of a task
at a fixed workload that can be expected of a system whose resources are
improved.

 The overall Speedup is the ratio of the execution time:-

Amdahl’s law and its proof

 The formula for Amdahl’s law is:

S = 1 / (1 – P + (P / N))
Where:
S is the speedup of the system
P is the proportion of the system that can be improved
N is the number of processors in the system

For example, if a system has a single bottleneck that occupies 20% of the total
execution time, and we add 4 more processors to the system, the speedup would
be:
S = 1 / (1 – 0.2 + (0.2 / 5))
S = 1 / (0.8 + 0.04)
S = 1 / 0.84
S = 1.19
This means that the overall performance of the system would improve by about 19%
with the addition of the 4 processors.
CPU Execution Time
MIPS in COA
Frequency
Memory Interfacing Example1
Memory Interfacing Example2
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Practice Problem on Addressing Modes
Create a data path that implements a single clock cycle approach to execute
the data transfer, arithmetic, and branching instructions.
Describe the schematic representation of a sequential multiplier that minimizes
the hardware needs for multiplying two numbers?
 Write a control sequence for an unconditional branching instruction, namely a
JUMP to memory address 4500 stored in register R1, for a single bus architecture.

• Z is the register and Zin and Zout are the input and output gating signal of register Z.
• Y is the register and Yin and Yout are the input and output signals of Y.
• MAR, or “Memory Address Register,” is part of a computer's central processing unit (CPU). CPUs possess memory addresses of data that must be fetched
and stored from or to the main memory. The memory address register is essential for data coordination and transfers between the CPU and memory.
• The Memory Data Register (MDR) in a computer system temporarily holds the data that is being transferred to or from the memory. During a read
operation, it stores the data fetched from the memory, and in a write operation, it holds the data ready to be stored in memory.
Write a control sequence for an unconditional branching instruction, namely a
JUMP to memory address 4500 stored in register R1, for a single bus architecture.

 The WMFC (Wait for Memory-Function-Completed) signal causes the

processor waits for the arrival of the MFC signal. The MFC (memory function
complete) signal is set by the addressed device when the contents of the
specified location have been read and are available on the data lines of the
memory bus.
 The IR is used to store the instruction word. When the CPU fetches an
instruction from memory, it is temporarily stored in the IR. The instruction is a
binary word or code that defines a specific operation to be performed. The
instruction word is also called the op code or operation code.
 The program counter, also known as the instruction pointer or simply PC, is a
fundamental component of a computer's central processing unit (CPU). It is a
special register that keeps track of the memory address of the next instruction
to be executed in a program.
Write the control sequence for instruction ADD R1, (R2) for indirect
addressing mode. Explain how microprogrammed control unit will generate
control sequence for the above-mentioned instruction.
Datapath is designed with 5 stage pipelining which are IF (Instruction Fetch),
D/R (Decode and Register Read), ALU, DM (Data Memory) and RW
(Register Write). If 3 instructions, I1 is R1+R2R3 and I2 is R3+R4R5
and I3 is R7+R8R9 is executed in a pipelined fashion. What type of hazard
is witnessed in which cycle when these instructions are executed in a
pipelined fashion, when we don’t add stall cycles. Calculate the number of
cycles required to execute the instruction without bypassing and with
bypassing / Data forwarding so that the various hazards can be eliminated.
Datapath is designed with 5 stage pipelining which are IF (Instruction Fetch),
D/R (Decode and Register Read), ALU, DM (Data Memory) and RW
(Register Write). If 3 instructions, I1 is R1+R2R3 and I2 is R3+R4R5
and I3 is R7+R8R9 is executed in a pipelined fashion. What type of hazard
is witnessed in which cycle when these instructions are executed in a
pipelined fashion, when we don’t add stall cycles. Calculate the number of
cycles required to execute the instruction without bypassing and with
bypassing / Data forwarding so that the various hazards can be eliminated.
Practice Problem on Booth’s Algorithm
 Compute +15 x -13 using the Booth’s Algorithm technique (assume size of
each register is 5 bits).
Practice Problem on Booth’s Algorithm
 Compute -9 x -13 using the Booth’s Algorithm technique (assume size of each
register is 5 bits).
Practice Problem on Pipelining
Practice Problem on Pipelining

Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given latch delay is
10 ns.

Part-02: Non-Pipeline Execution Time-

Non-pipeline execution time for one instruction

= 60 ns + 50 ns + 90 ns + 80 ns
= 280 ns

Part-03: Speed Up Ratio-

Speed up = Non-pipeline execution time / Pipeline execution time

= 280 ns / Cycle time
= 280 ns / 100 ns
= 2.8
Practice Problem on Pipelining
Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given latch delay is 10 ns.
Part-04: Pipeline Time For 1000 Tasks-

Pipeline time for 1000 tasks = Time taken for 1st task + Time taken for
remaining 999 tasks
= 1 x 4 clock cycles + 999 x 1 clock cycle
= 4 x cycle time + 999 x cycle time
= 4 x 100 ns + 999 x 100 ns
= 400 ns + 99900 ns
= 100300 ns
Part-05: Sequential Time For 1000 Tasks-

Non-pipeline time for 1000 tasks = 1000 x Time taken for one task
= 1000 x 280 ns
= 280000 ns
Practice Problem on Pipelining

Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given
latch delay is 10 ns.

Part-06: Throughput-

Throughput for pipelined execution = Number of

instructions executed per unit time
= 1000 tasks / 100300 ns
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average
cycles per instruction of 4. The same processor is upgraded to a pipelined processor
with five stages but due to the internal pipeline delay, the clock speed is reduced to 2
gigahertz. Assume there are no stalls in the pipeline. The speed up achieved in this
pipelined processor is-
Non-Pipeline Execution Time-
Non-pipeline execution time to process 1 instruction = Number of clock
cycles taken to execute one instruction
= 4 clock cycles
= 4 x 0.4 ns
= 1.6 ns
Cycle Time in Pipelined Processor- Frequency of the clock = 2 gigahertz
Cycle time = 1 / frequency
= 1 / (2 gigahertz)
= 1 / (2 x 109 hertz)
= 0.5 ns
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
The stage delays in a 4 stage pipeline are 800, 500, 400 and 300 picoseconds.
The first stage is replaced with a functionally equivalent design involving two
stages with respective delays 600 and 350 picoseconds. The throughput
increase of the pipeline is _____%.
Execution Time in 2 Stage Pipeline-
Cycle time = Maximum delay due to any stage + Delay due to its
register
= Max { 600, 350 } + 0
= 600 picoseconds
Thus, Execution time in 2 stage pipeline = 1 clock cycle = 600 picoseconds.

Throughput in 2 Stage Pipeline-

Throughput = Number of instructions executed per unit time
= 1 instruction / 600 picoseconds
Practice Problem on Pipelining
The stage delays in a 4 stage pipeline are 800, 500, 400 and 300
picoseconds. The first stage is replaced with a functionally equivalent
design involving two stages with respective delays 600 and 350
picoseconds. The throughput increase of the pipeline is _____%.

Throughput Increase = { (Final throughput – Initial

throughput) / Initial throughput } x 100
= { (1 / 600 – 1 / 800) / (1 / 800) } x 100
= { (800 / 600) – 1 } x 100
= (1.33 – 1) x 100
= 0.3333 x 100
= 33.33 %
Practice Problem on Pipelining
Practice Problem on Pipelining
A non-pipelined single cycle processor operating at 100 MHz is converted into a
synchronous pipelined processor with five stages requiring 2.5 ns, 1.5 ns, 2 ns, 1.5 ns
and 2.5 ns respectively. The delay of the latches is 0.5 nsec.
Non-Pipeline Execution Time-
Non-pipeline execution time to process 1 instruction = Number of clock
cycles taken to execute one instruction
= 1 clock cycle
= 0.01 μs
= 10 ns

Cycle Time in Pipelined Processor-

Cycle time = Maximum delay due to any stage + Delay due to its register
= Max { 2.5, 1.5, 2, 1.5, 2.5 } + 0.5 ns
= 2.5 ns + 0.5 ns
= 3 ns
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 has
5 stage pipeline with execution time of 3 ns, 2 ns, 4 ns, 2 ns and 3 ns. While
the design D2 has 8 pipeline stages each with 2 ns execution time. How
much time can be saved using design D2 over design D1 for executing 100
instructions?

Execution Time For 100 Instructions in Design D1-

Execution time for 100 instructions = Time taken for 1 st instruction
+ Time taken for remaining 99 instructions
= 1 x 5 clock cycles + 99 x 1 clock cycle
= 5 x cycle time + 99 x cycle time
= 5 x 4 ns + 99 x 4 ns
= 20 ns + 396 ns
= 416 ns
 Practice Problem on Pipelining
We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 has 5 stage
pipeline with execution time of 3 ns, 2 ns, 4 ns, 2 ns and 3 ns. While the design D2 has 8
pipeline stages each with 2 ns execution time. How much time can be saved using
design D2 over design D1 for executing 100 instructions?
Cycle Time in Design D2-
Cycle time = Delay due to a stage + Delay due to its register
= 2 ns + 0
= 2 ns
Execution Time For 100 Instructions in Design D2-
Execution time for 100 instructions = Time taken for 1st instruction + Time
taken for remaining 99 instructions
= 1 x 8 clock cycles + 99 x 1 clock cycle
= 8 x cycle time + 99 x cycle time
= 8 x 2 ns + 99 x 2 ns
= 16 ns + 198 ns
= 214 ns
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
Practice Problem on Pipelining
Direct Memory Mapping – Example1
Direct Memory Mapping – Example1
Direct Memory Mapping – Example2
Direct Memory Mapping – Example3
Associative Mapping – Example1
Set Associative Mapping – Example1
Set Associative Mapping – Example1
Practice Problem on Interleaved Memories
Practice Problem on Interleaved Memories
Practice Problem on Interleaved Memories
Practice Problem on Interleaved Memories
 Dr. SHAKTI KUNDU

Computer Organization &Architecture

2025