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Design and Verification of RISC-V processor for DSP applications

Major Project Presentation

Anil Darga 1RV21EC020

Mallikarjun Awwanna Teli
1RV21EC092
Shashank Otihal 1RV21EC156
Shashank KC 1RV21EC157

Guide Name: Dr M Govinda Raju

Designation: Associate Professor
Department of Electronics and Communication Engineering

1
18/03/2025
 Outline

• Introduction
• Motivation
• Problem Statement
• Objectives of the project
• Literature Survey
• Methodology
• Project Timeline
• References
 Introduction
• Modern signal processing applications like surveillance systems, autonomous robots, medical
imaging, and IoT edge devices, efficient and low-power image processing is crucial.

• These systems often rely on simple black-and-white (BW) image operations such as
edge detection, masking, and pattern recognition.
• Performing such tasks directly on resource-constrained processors requires optimised,
low-level code.
• Performance of these image-processing operations on two RISC-V architectures: RV32I
and RV32P (SIMD) depends on factors like instruction-level parallelism, memory access
latency, and processing throughput.
 Introduction

• RV32I processes instructions sequentially, RV32P supports parallel execution through SIMD
extensions, which can significantly enhance performance for data-parallel tasks like image
processing.

• This project begins by converting a BW image into a 2D array in C, performing operations like
edge detection, and compiling the logic into .o, .bin, .mem files.

• These .mem files represents the machine code than can be directly implemented into RISC-V
simulators and analyse the performance of processor.
 Motivation
• Traditional processors often struggle with the computational intensity of pixel-level
operations in real-time systems.

• RISC-V offers a modular, open-source instruction set architecture suitable for domain-
specific optimization.

• RV32P, with SIMD (Single Instruction Multiple Data) extensions, promises significant
speedups for image-based computations compared to the baseline RV32I.

• Analysing processor behaviour for various image processing tasks helps in identifying
performance bottlenecks and improvement areas.
 Problem Statement:

Efficient image processing is essential in modern DSP applications, yet scalar architectures like
RV32I struggle with performance and energy efficiency. While RV32P introduces SIMD
capabilities for parallelism, a clear performance comparison using real image-derived
instructions is lacking.
 Objectives of the Project

1. Design a RISC-V datapath that supports P extension(Packed SIMD) for DSP.

2. To create Bring-up test programs to design and validate the functionality of instructions.
3. To implement the edge detection on the designed processor.
4. To compare the speed of RV32IP with respect to RV32I.
 Literature Survey
Sl No Paper Title, Journal Name, Year Major findings / observations

1 Pal, S.; Roy, A.; Bhunia, S. “RISC-V Based Hardware Accelerator for Introduced a RISC-V based hardware
Edge Detection in Images”, IEEE Access, 2021022. accelerator for Sobel edge detection,
achieving high performance and low
power for embedded systems.

2 Asanović, K.; Patterson, D. A.; Waterman, A. “The RISC-V Instruction Provided a modular and open-source ISA
Set Manual Volume I: User-Level ISA”, UCB Tech Report, 2019 design for RISC-V, forming the basis for
widespread academic and industrial
adoption.
 Literature Survey
Sl No Paper Title, Journal Name, Year Major findings / observations
3 Lee, Y.; Kim, D.; Yoo, S. “Exploring the Design Space of RISC-V SIMD Evaluated RISC-V SIMD extensions,
Extensions for Image and Signal Processing”, IEEE Micro, 2021 showing significant speedup in image
and signal processing through
parallelism.

4 Chen, Y.; Gao, Y.; Zhang, L. “Design and Evaluation of SIMD Explores multiple SIMD design
Extensions for RISC-V Processors”, IEEE Transactions on Computers, approaches for RISC-V processors, and
2021. shows improved performance in DSP
workloads with P-extension support.
 Literature Survey
Sl No Paper Title, Journal Name, Year Major findings / observations
5 Hela Belhadj Amor, Carolynn Bernier, and Zdenek Prikryl, “A RISC-V ISA Introduces a RISC-V ISA extension
Extension for Ultra-Low Power IoT Wireless Signal Processing”, IEEE optimised for ultra-low power wireless
TRANSACTIONS ON COMPUTERS, VOL. 71, NO. 4, APRIL 2022. signal processing. Demonstrates
significant energy efficiency
improvements for IoT applications
without compromising performance.

6 Stefan Tönsing and Michael Hübner, “Image Processing on High Explores the integration of image
Performance RISC Systems”, IEEE International Parallel and Distributed processing algorithms on high-
Processing Symposium Workshops (IPDPSW), 2016. performance RISC-based systems.
Demonstrates that RISC architectures,
when properly optimised, can achieve
real-time performance in image
processing tasks.
Design Methodology
RV32I pipelined processor with Hazard unit
 Details of Software / Hardware

● Iverilog and GTK wave for compiling Verilog and seeing the waveforms
● VS code IDE for coding
● RISC-V GCC tool chain
Timeline of the Project
 References

Sl No Author, Title of paper, Journal Year

Hela Belhadj Amor, Carolynn Bernier, Zdenek Prikryl, A RISC-V ISA Extension for Ultra-Low Power
1 2022
IoT Wireless Signal Processing, IEEE Transactions on Computers.

Martin, A., Robles, J., Implementing SIMD Image Filters Using RISC-V Vector and Packed
2 2022
Extensions on FPGAs, Journal of Systems Architecture.

Pal, S., Roy, A., Bhunia, S., RISC-V Based Hardware Accelerator for Edge Detection in Images,
3 2021
IEEE Access.

Lee, Y., Kim, D., Yoo, S., Exploring the Design Space of RISC-V SIMD Extensions for Image and
4 2021
Signal Processing, IEEE Micro.

hen, Y., Gao, Y., Zhang, L., Design and Evaluation of SIMD Extensions for RISC-V Processors,
5 2021
IEEE Transactions on Computers.
Sl No Author, Title of paper, Journal Year
Waterman, A., Asanović, K., The RISC-V Instruction Set Manual Volume II: Privileged Architecture,
6 2021
UCB Tech Report.

Asanović, K., Patterson, D. A., Waterman, A., The RISC-V Instruction Set Manual Volume I: User-
7 2020
Level ISA, University of California, Berkeley (Tech. Rep.).

Zhang, T., Lin, Y., Yang, H., Efficient Binary to Memory Conversion Techniques for Embedded
8 2020
Systems, IEEE TCAD.

Schaffner, M., Traber, A., Capotondi, A., Pullini, A., Benini, L., VXU: A RISC-V Vector Processing Unit
9 2019
for FPGA-Accelerated Edge Computing, DATE Conference Proceedings.

maragdos, G., Stamatakis, S., Papadimitriou, K., Soudris, D., A RISC-V Platform for Reconfigurable
10 2019
Computing, ACM TECS.
Thank You