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Instruction Formats: - Memory and Branch Instructions

The document outlines the instruction formats for a control unit, detailing memory and branch instructions, register reference instructions, and input/output instructions. It describes how instructions are structured, including opcode and addressing schemes, and emphasizes the importance of distinguishing between different types of instructions for effective decoding. Additionally, it explains the design of the control unit, including the use of a sequence counter for timing signals and instruction execution sequencing.

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5 views17 pages

Instruction Formats: - Memory and Branch Instructions

The document outlines the instruction formats for a control unit, detailing memory and branch instructions, register reference instructions, and input/output instructions. It describes how instructions are structured, including opcode and addressing schemes, and emphasizes the importance of distinguishing between different types of instructions for effective decoding. Additionally, it explains the design of the control unit, including the use of a sequence counter for timing signals and instruction execution sequencing.

Uploaded by

elinahishaq
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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Instruction Formats

• Memory and Branch Instructions.


– Direct/Indirect addressing (1-bit for flag).
– 12 bit address field.
– 7 instructions, 3 bits are needed for the opcode.
– 16-bit instruction.
15 14 12 11 0

I OPCODE ADDRESS

– All instructions will be 16-bits.


Register Reference Instructions.
– Can use all 16-bits for opcode.
– However, must clearly distinguish these
instructions from memory reference.
• Use a unique prefix for register reference
instruction.
– The opcode combination 1 1 1 is unused in memory
reference instructions.
– Use it with a 0 in the Direct/Indirect field to identify
register reference instructions.
15 11 0

0 1 1 1 OPERATION
Input/Output and Interrupt instructions.
– No possibility to provide port number in the
instruction.
– Can use all 16-bits of the instruction to specify the
opcode.
– However, must clearly distinguish these instructions
from memory and register reference.
• Use the combination 1 1 1 for the opcode with a 1 in the
Direct/Indirect field.

15 11 0

1 1 1 1 OPERATION

• These instructions will all begin with an F.


Memory and Branch Instructions
15 11 0

I OPCODE ` ADDRESS

Operation Direct Indirect


AND 0xxx 8xxx
ADD 1xxx 9xxx
LDA 2xxx Axxx
STA 3xxx Bxxx
BUN 4xxx Cxxx
BSA 5xxx Dxxx
ISZ 6xxx Exxx
Register Reference Instructions
Operations OPCODE
15 11 0 CLA 7800
0 1 1 1 OPERATION CLE 7400
CMA 7200
• We will use a different CME 7100
bit in the operation CIR 7080
field to signify the CIL 7040
INC 7020
different instructions.
SPA 7010
– This will greatly
SNA 7008
simplify the instruction
decoding scheme. SZA 7004
SZE 7002
HLT 7001
I/O Instructions
Operations OPCODE
15 11 0
INP F800
1 1 1 1 OPERATION
OUT F400
SKI F200
• We will use a SKO F100
different bit in the ION F080
operation field to IOF F040
signify the different
instructions.
– This will greatly
simplify the
instruction decoding
scheme.
Design of Control Unit

The Hardwired Implementation


Control Unit Design
• It can be seen very easily that the Instruction
register is central to the operation of the Control
Unit.
– Instructions read from memory are stored in IR
– The contents of IR are decoded to determine what
operations are to be executed next.

• The control unit can be thought of as the IR


surrounded by several decoders.
Decoding the instruction
IR 15 14 13 12 11 - 0

3 to 8 Decoder
7 6 5 4 3 2 1 0

I Control
Control
Logic
Signals
Decoding the instruction
• In our instruction format design, the instruction is
decoded in the following steps:
– Decode bits 12 – 14 of the instruction.
• If they are equal to 7, the instruction is “non-memory”
– If bit 15 is 0, then register transfer, look at bits 0 – 11 to
determine the operation.
– Else, the input/output operation, look at bits 0 – 11 for the
operation.
• Else, the instruction is “memory”
– If bit 15 is 0, then direct memory reference, bits 0 – 11 contain
the effective address
– Else, indirect memory reference, bits 0 – 11 contain the address
of the memory location containing the effective address
Timing Signals
• Each instruction is made up of several micro-
operations that need to be executed in sequence.
– A mechanism is needed to allow the sequencing of these
operations,this requires timing signals.
– The solution is a “sequence counter”. This along with the
decoder provides the timing signals.
• Similar to the program counter. Except that it sequences at the
micro-operation level within the instruction.
– How large?
• Depends on the complexity of the instructions.
• Needs to generate enough combinations to allow sequencing the
most complex instruction.
Sequencing the execution
IR 15 14 13 12 11 - 0

3 to 8 Decoder
7 6 5 4 3 2 1 0
D0
I
D7

Control
Control
T15 Logic
Signals

T0
15 14 2 1 0
4 to 16 Decoder

4-bit Increment
Sequence
Counter Clear
The Sequence Counter
• In our example we will use a 4-bit sequence counter.
– It will generate 16 different combinations allowing a
maximum of 16 different micro-operations within an
instruction.
– This counter is automatically incremented at the end of
each micro-operation.
– The last micro-operation of the instruction will reset the
counter to 0 to initiate the execution of the next
instruction.
– The counter’s output will be decoded and fed into the
control logic.
The Sequence Counter
• As an example consider the case where SC is
incremented to provide timing signals T0,T1,T2,
T3 and T4 in sequence. At time T4, SC is cleared
to 0 if decoder output D3 is active. This is
expressed as:

D3T4: SC 0

• The timing diagram on next slide shows the time


relationship of the control signals
Initially the CLR input of SC is
active. The first positive transition
of the clock clears SC to 0, which in
turn activates the timing signal T0
out of the decoder. T0 is active
during one clock cycle.

The positive clock transition labeled


T0 in the diagram will trigger only
those registers whose control inputs
are connected to the timing signal T0.

SC is incremented every positive


clock transition unless its CLR input
is active. This produces the sequence
of timing signals T0, T1, T2, T3, T4
and so on.
The last three
waveforms show
how SC is cleared
when D3T4=1
When timing signal T4
becomes active the
output of the AND
Gate that implements
the control function
D3T4 becomes active.
This is applied to the
CLR input of the SC.

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