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Sequential Circuits

The document outlines the differences between combinational and sequential circuits, emphasizing that sequential circuits depend on both present and previous inputs, while combinational circuits rely solely on present inputs. It details various types of flip-flops (S-R, JK, D, and T) using NAND gates, including their truth tables, characteristic equations, and excitation tables. The document serves as a comprehensive guide to understanding the fundamental concepts and operations of sequential circuits.

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4 views14 pages

Sequential Circuits

The document outlines the differences between combinational and sequential circuits, emphasizing that sequential circuits depend on both present and previous inputs, while combinational circuits rely solely on present inputs. It details various types of flip-flops (S-R, JK, D, and T) using NAND gates, including their truth tables, characteristic equations, and excitation tables. The document serves as a comprehensive guide to understanding the fundamental concepts and operations of sequential circuits.

Uploaded by

pranalipat23
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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SEQUENTIAL CIRCUITS

SHUBHAM SUBHASH GHADIGAONKAR


Difference between
Combinational circuit and sequential circuit

Combinational circuit Sequential circuit


1. Present output depends on 1. Present input depends on
present input. present input and previous
2. Combinational circuit is time inputs/outputs.
in-dependent, don't have a 2. Sequential circuit is time
clock signal dependent, have got a clock
3. Ex:- adder, subtracter signal
3. Ex:- Flip-flops, counters etc.
S-R Latch using NAND gate
A B Y= A.B
0 0 1
0 1 1
1 0 1
1 1 0
Truth table@NAND gate

S R Q(n+1)
0 0 NOT VALID
0 1 1
1 0 0
1 1 HOLD

Truth table@S-R latch


What is a clock?
S-R Flip-Flop using NAND gate
S R Q(n+1)
0 0 NOT VALID
0 1 1
1 0 0
1 1 HOLD
Truth table@S-R latch
Clock S R Q(n+1)
Not -- -- No change
triggered
Triggered 0 0 HOLD
Triggered 0 1 0
Triggered 1 0 1
Triggered 1 1 Invalid
Truth table@S-R flip-flop
JK Flip-Flop using NAND gate
The JK flip flop is basically a gated SR flip-
flop with the addition of a clock input
circuitry that prevents the illegal or invalid
output condition that can occur when both
inputs S and R are equal to logic level “1”.
Due to this additional clocked input, a JK
flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no
Truth table @JK Flip-Flop change” and “toggle”.

CLK J K Q(n+1)
0 X X Qn/HOLD
1 0 0 Qn/HOLD
1 0 1 0
1 1 0 1
1 1 1 Toggle
Characteristic table @JK Flip-Flop

Qn j k Q(n+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Q(n+1) K-Map
JK 00 01 11 10
Qn
0 0 0 1 1
Characteristic equation
1 1 0 0 1
Q(n+1)= Qn J + Qn k
Excitation table @JK
Flip-Flop
Qn Q(n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Excitation equation
J = Q(n+1) K= Q(n+1)
D Flip-Flop using NAND gate
D Flip-Flop also called as Delay Flip-Flop or Data Flip-Flip, provides same
output as given input in next Q(n+1) state.
Logic table @D-
Flip Flop
CLK D Q(n+1)

0 X Qn

1 0 0

1 1 1

We get same output I.e. Q(n+1) as input D


Characteristic table @D Flip-Flop
Qn D Q(n+1)
0 0 0
Characteristic equation
0 1 1 Q(n+1) = D
1 0 0
1 1 1

Excitation table @D Flip-Flop


Qn Q(n+1) D
0 0 0
Excitation equation
0 1 1 D = Q(n+1)
1 0 0
1 1 1
T Flip-Flop using NAND gate
The T flip-flop is also called toggle flip-flop. T flip flop is received by shorting both
inputs of a JK flip-flop. When T = 0 there is no change in the output. When T= 1, the
output toggles.
Logic table @T-
flip
CLK
flop T Q(n+1)
0 X Qn
1 0 Qn
1 1 Toggle

Characteristic table @T-flip flop


Qn T Q(n+1)
0 0 0 Characteristic equation
0 1 1 Q(n+1) = Qn + T
1 0 1
1 1 0
Excitation table @T-Flip flop
Qn Q(n+1) T
0 0 0
0 1 1
1 0 1
1 1 0

Excitation equation
T = Qn + Q(n+1)

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