Digital Design and

Computer Organization
(BCS302)

Module – 4:
Input / Output Organization
Syllabus:
Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and Disabling
Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size and Cost of
memory systems. Cache Memories – Mapping Functions.

Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1

Text books:
1. M. Morris Mano & Michael D. Ciletti, "Digital Design With an Introduction to Verilog Design", 5e,
Pearson Education.
2. Carl Hamacher, ZvonkoVranesic, SafwatZaky, "Computer Organization", 5th Edition, Tata McGraw Hill

Mohan A R, VCET Puttur

Accessing I/O Devices:
Single-bus structure:
 The bus enables all the devices connected to it to exchange information
 Multiple I/O devices may be connected to the processor and the memory via a bus.
 Bus consists of three sets of lines to carry address, data and control signals.
 Each I/O device is assigned an unique address.
 To access a particular I/O device, the
processor places the address on the address
lines.
 The device that recognizes the address, and
responds to the control signals.
 The processor requests can be either a read or a write
operation, and the requested data are transferred over
the data lines.
Single-Bus structure
Mohan A R, VCET Puttur
Accessing I/O Devices:
 I/O device is connected to the bus using an I/O
interface circuit which has
i. Address decoder
ii. Control Circuits
iii. Data and status register
I/O interface for an input device
 The address decoder enables the device to recognize its address when this address appears on the address lines.
 The data register holds the data being transferred to or from the processor.
 The status register contains information relevant to the operation of the I/O device.
 Both the data and status registers are connected to the data bus and assigned unique addresses.
 The address decoder, the data and status registers, and the control circuitry required to coordinate transfers
constitute the device's interface circuit.
Mohan A R, VCET Puttur
Memory-Mapped I/O:
 When I/O devices and the memory share the same address space, the arrangement is called memory-
mapped I/O.

 Any machine instruction that can access memory can be used to transfer data to or from an I/O
device.

 For example, if DATAIN is the address of the input buffer associated with the keyboard, the instruction

Move DATAIN, R0 ; reads the data from DATAIN and stores them into processor
register R0.
 Similarly, if DATOUT is the address of the output data buffer associated with a display unit or a printer, the
instruction
Move R0, DATAOUT ; sends the contents of register R0 to location DATAOUT, which may be the output
; data buffer of a display unit or a printer.
 Some processors have special In and Out instructions to perform I/O transfer.
Mohan A R, VCET Puttur
Mechanisms used for Interfacing I/O Devices:
Program Controlled I/O:
 Processor repeatedly checks a status-flag to achieve required synchronization between processor &
input/output device. (Processor polls the I/O device).
 Main drawback: The processor wastes its time in checking the status of the device before actual data
transfer takes place.
Interrupt I/O:
 Synchronization is achieved by having I/O device send a special signal over bus whenever it is ready
for a data transfer operation.
Direct Memory Access (DMA):
 Technique used for high speed I/O devices.
 It has a device-interface which transfer data directly to or from the memory without continuous
involvement by the processor.
Mohan A R, VCET Puttur
Program Controlled I/O - Example:
 Consider a simple example of I/O operations involv­ing a keyboard and a display device in a computer system.
 Four registers are used in the data transfer operations.
 Data from the keyboard are made available in the DATAIN register, and data sent to the display are stored in
the DATAOUT register.
 Register STATUS contains
 Two control flags, SIN and SOUT, which provide status information for the keyboard and the display
unit, respectively.
 Two flags KIRQ and DIRQ are the
interrupt request bits.
 The KEN and DEN bits in CON­TROL register
used to enable keyboard and display interrupt

Mohan A R, VCET Puttur

Program Controlled I/O - Example:
Program that reads one line from the keyboard, stores it in memory buffer, and echoes it back to the display.

Mohan A R, VCET Puttur

Interrupts:
 In program-controlled I/O, when the processor continuously monitors the status of the device, it does

not perform any useful tasks.

 An alternate approach would be for the I/O device to alert the processor when it becomes ready.

 Done by sending a hardware signal called an interrupt to the processor.

 At least one of the bus control lines, called an interrupt-request line is dedicated for this purpose.

 Processor can perform other useful tasks while it is waiting for the device to be ready

Mohan A R, VCET Puttur

Interrupts:
 Processor is executing the instruction located at address i when an interrupt occurs.
 Routine executed in response to an interrupt request is called the interrupt-service routine.
 When an interrupt occurs, control must be transferred to the interrupt service routine.

 But before transferring control, the current contents

of the PC (i+1), must be saved in a known location.
 This will enable the return-from-interrupt
instruction to resume execution at i+1.

 Return address, or the contents of the PC

are usually stored on the processor stack. Transfer of control through the use of interrupts
Mohan A R, VCET Puttur
Interrupts:
 Consider a task that requires some computations to be performed and the results to be printed on a line
printer.
 Let the program consist of two routines, COMPUTE and PRINT.

 Assume that COMPUTE produces a set of n

lines of output, to be printed by the PRINT
routine.
 First, the COMPUTE routine is executed to
produce the first n lines of output.

 Then, the PRINT routine is executed to

send the first line of text to the printer.
Transfer of control through the use of interrupts
Mohan A R, VCET Puttur
Interrupts:
 Saving and restoring information can be done automatically by the processor or explicitly by program
instructions.
 The information that needs to be saved and restored typically includes the condition code flags and
the contents of any registers used by both the interrupted program and the interrupt-service routine
 Saving and restoring registers involves memory transfers:
 Increases the total execution time.
 Increases the delay between the time an interrupt request is received, and the start of execution of
the interrupt-service routine. This delay is called interrupt latency.
 In order to reduce the interrupt latency, most processors save only the minimal amount of information:
 This minimal amount of information includes Program Counter and processor status registers.
 Any additional information that must be saved, must be saved explicitly by the program instructions at
the beginning of the interrupt service routine.
Mohan A R, VCET Puttur
Interrupt Hardware:
 An I/O device requests an interrupt by activating a bus line called interrupt-request.
 Most computers are likely to have several I/O devices that can request an interrupt.
 A single interrupt-request line may be used to serve n devices as shown.
 All devices are connected to the line via switches to ground. To request an interrupt, a device closes its
associated switch.
 Thus, if all interrupt-request signals INTR1
to INTRn are inactive, that is, if all
switches are open, the voltage on the
interrupt-request line will be equal to 𝑉𝑑𝑑.
 This is the inactive state of the line.

Mohan A R, VCET Puttur

Interrupt Hardware:
 When a device requests an interrupt by closing its switch, the voltage on the line drops to 0, causing the
interrupt-request signal, INTR, received by the processor to go to 1.
 The value of INTR is the logical OR of the requests from individual devices
INTR = INTR1 + INTR2 + . . . . . + INTRn

 Resistor R is called a pull-up resistor

because it pulls the line voltage up to the
high-voltage state when the switches are
open.

Mohan A R, VCET Puttur

Enabling & Disabling Interrupts:
 To prevent the system from entering into an infinite-loop because of interrupt, there are 3 possibilities:
1. The first possibility is to have the processor-hardware ignore the interrupt-request line until the
execution of the first instruction of the ISR has been completed.
 First instruction of an interrupt service routine can be Interrupt-disable.
 Last instruction of an interrupt service routine before the Return-from-interrupt instruction can
be Interrupt-enable.
 The processor must guarantee that execution of the Return-from-interrupt instruction is
completed before further interruption can occur.

Mohan A R, VCET Puttur

Enabling & Disabling Interrupts:
2. The second option is to have the processor automatically disable interrupts before starting the
execution of the ISR.
 One bit in the PS (Program Status) register, called Interrupt-enable, indicates whether
interrupts are enabled.
 An interrupt request received while this bit is equal to 1 will be accepted.
 After saving the contents of the PS on the stack, with the Interrupt-enable bit equal to 1, the
processor clears the Interrupt-enable bit in its PS register, thus disabling further interrupts.
 When a Return-from-interrupt instruction is executed, the contents of the PS are restored from
the stack, setting the Interrupt-enable bit back to 1.
 Hence, interrupts are again enabled.

Mohan A R, VCET Puttur

Enabling & Disabling Interrupts:
3. In the third option, the processor has a special interrupt-request line for which the interrupt-handling
circuit responds only to the leading edge of the signal. Such a line is said to be edge-triggered.
 In this case, the processor will receive only one request, regardless of how long the line is
activated.
 Hence, there is no danger of multiple interruptions and no need to explicitly disable interrupt
requests from this line.

Mohan A R, VCET Puttur

Events involved in handling an interrupt-request:
 Sequence of events involved in handling an interrupt-request from a single device is as follows:

1. The device raises an interrupt-request.

2. The program currently being executed is interrupted.

3. All interrupts are disabled(by changing the control bits in the PS).

4. The device is informed that its request has been recognized, and in response, the device

deactivates the interrupt-request signal.

5. The action requested by the interrupt is performed by the ISR.

6. Interrupts are enabled again and execution of the interrupted program is resumed.

Mohan A R, VCET Puttur

Handling Multiple Devices:
 When a request is received over the common interrupt-request line, additional information is needed to
identify the particular device that activated the line.
 Furthermore, if two devices have activated the line at the same time, it must be possible to break the tie and
select one of the two requests for service.
 When the interrupt-service routine for the selected device has been completed, the second request can be
serviced.

 The information needed to determine

whether a device is requesting an interrupt
is available in its status register.

Mohan A R, VCET Puttur

Handling Multiple Devices:
 The status register of each device has an IRQ bit which it sets to 1 when it requests an interrupt.
 For example, bits KIRQ and DIRQ are the interrupt request bits for the keyboard and the display,
respectively.
 Interrupt service routine can poll the I/O devices connected to the bus.
 The first device with IRQ equal to 1 is the one that is serviced.
 Polling mechanism is easy, but time consuming to query the status bits of all the I/O devices connected to
the bus.

Mohan A R, VCET Puttur

Vectored Interrupts:
 A device requesting an interrupt can identify itself by sending a special code to the processor over the bus.
 This enables the processor to identify individual devices even if they share a single interrupt-
request line.
 The code supplied by the device may represent the starting address of the interrupt-service routine for that
device.
 The code length is typically in the range of 4 to 8 bits.
 The remainder of the address is supplied by the processor based on the area in its memory where
the addresses for interrupt-service routines are located.
 This arrangement implies that the interrupt-service routine for a given device must always start at the same
location.

Mohan A R, VCET Puttur

Vectored Interrupts:
 Usually the location pointed to by the interrupting device is used to store the starting address of the

interrupt-service routine.

 The processor reads this address, called the interrupt vector, and loads it into the PC.

 In most computers, I/O devices send the interrupt-vector code over the data bus.

 The interrupting device must wait to put data on the bus only when the processor is ready to receive it.

 When the processor is ready to receive the interrupt-vector code, it activates the interrupt-acknowledge line,

INTA.

 The I/O device responds by sending its interrupt-vector code and turning off the INTR signal.

Mohan A R, VCET Puttur

Interrupt Priority:
 A multiple-priority scheme can be implemented easily by using separate interrupt-request and interrupt-
acknowledge lines for each device
 Each of the interrupt-request lines is assigned a different priority level.
 Interrupt requests received over these lines are sent to a priority arbitration circuit in the processor.
 A request is accepted only if it has a higher priority level than that currently assigned to the
processor.
 A priority level is assigned to a processor that
can be changed under program control.
 Processor’s priority is encoded in a few bits
of the processor status register.
 Priority can be changed by instructions that
write into the processor status register.
Mohan A R, VCET Puttur
Simultaneous Requests:
Daisy chain scheme:
 Devices are connected to form a daisy chain. The interrupt-request line is common to all devices
 Interrupt-acknowledge line INTA is connected in a daisy-chain fashion.
 When devices raise an interrupt request, the interrupt-request line is activated.
 The processor responds by setting INTA line to 1
 This signal is received by device 1; if device 1 does not need service, it passes the signal to device 2.
 If device 1 has a pending request for interrupt, it blocks the INTA signal and proceeds to put its identifying
code on the data lines.
 Device that is electrically
closest to the processor has
the highest priority.

Mohan A R, VCET Puttur

Priority Group:
 Devices are organized into groups.
 Each group is assigned a different priority level.
 All the devices within a single group share an interrupt-request line and interrupt-acknowledge lines and are
connected to form a daisy chain.

Mohan A R, VCET Puttur

Direct Memory Access (DMA):
 The transfer of a block of data directly between an external device & main memory without continuous
involvement by processor is called as DMA.
 DMA controller performs the functions that
would normally be carried out by processor
 In controller, 3 registers are accessed by
processor to initiate transfer operations
 Two registers are used for storing
starting-address & word-count
 Third register contains status- &
control-flags

Mohan A R, VCET Puttur

Direct Memory Access (DMA):
 The R/W bit determines direction of transfer.
 When R/W = 1, controller performs a read operation (i.e. it transfers data from memory to I/O device)
 When R/W = 0, controller performs a write operation (i.e. it transfers data from I/O device to memory).
 When Done = 1, controller
 completes transferring a block of data & is ready to receive another command.
 When IE = 1, controller raises an interrupt after it has completed transferring a block of data (IE = Interrupt
Enable).
 When IRQ=1, controller requests an
interrupt. (Requests by DMA devices
for using the bus are always given
higher priority than processor
requests).
Mohan A R, VCET Puttur
Direct Memory Access (DMA):
 There are 2 ways in which the DMA operation can be carried out:
 In one method, processor originates most memory-access cycles. DMA controller is said to "steal"
memory cycles from processor. Hence, this technique is usually called cycle stealing.
 In second method, DMA controller is given exclusive access to main-memory to transfer a block of
data without any interruption. This is known as block mode (or burst mode).

Mohan A R, VCET Puttur

BUS Arbitration:
 A conflict may arise if both the processor and a DMA controller or two DMA controllers try to use the bus
at the same time to access the main memory. To resolve this problem, an arbitration procedure on bus is
needed
 The device that is allowed to initiate data transfer on the bus at any given time is called the bus master.
When the current master relinquishes control of the bus, another device can acquire this status.
 Bus arbitration is the process by which the next device to become the bus master take into account the
needs of various devices by establishing a priority system for gaining access to the bus
 There are two approaches to bus arbitration
i. Centralized - a single bus arbiter performs the required arbitration
ii. Distributed - all devices participate in the selection of the next bus master

Mohan A R, VCET Puttur

Centralized Arbitration:
 A single bus-arbiter performs the required arbitration process.
 Normally, processor is the bus master unless it grants bus mastership to one of the DMA controllers.

 A DMA controller indicates that it needs to

become bus master by activating Bus-Request
line(BR).
 The signal on the BR line is the logical OR of
bus-requests from all devices connected to it.
 When BR is activated, processor activates Bus-
Grant signal (BG1) indicating to DMA
controllers that they may use bus when it
becomes free. (connected to all DMA
controllers using a daisy-chain arrangement).
Mohan A R, VCET Puttur
Centralized Arbitration:
 If DMA controller-1 is requesting the bus, it blocks propagation of grant-signal to other devices. Otherwise,
it passes the grant downstream by asserting BG2.

 Current bus-master indicates to all devices that

it is using bus by activating Bus-Busy line
(BBSY).
 Arbiter circuit ensures that only one request is
granted at any given time according to a
predefined priority scheme

Mohan A R, VCET Puttur

Distributed Arbitration:
 All device participate in the selection of next bus-master. Each device on bus is assigned a 4-bit
identification number (ID).
 When 1 or more devices request bus, they assert
signal & place their 4-bit ID numbers on four open-
collector lines through .
 A winner is selected as a result of interaction among
signals transmitted over these lines by all contenders.
 Net outcome is that the code on 4 lines represents
request that has the highest ID number.
 Main advantage: This approach offers higher
reliability since operation of bus is not dependent on
any single device.
Distributed Arbitration scheme
Mohan A R, VCET Puttur
Speed, Size, and Cost:
 A big challenge in the design of a computer system is to provide a sufficiently large memory, with a
reasonable speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a complex circuit making it impossible to
pack a large number of cells onto a single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive, but significantly slower than SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is still less than what is necessary.
 Secondary storage such as magnetic disks provide a large amount of storage, but is much slower
than DRAMs.

Mohan A R, VCET Puttur

Memory Hierarchy:
 Fastest access is to the data held in processor registers.
Registers are at the top of the memory hierarchy.
 Relatively small amount of memory that can be
implemented on the processor chip. This is processor
cache.
 Two levels of cache.
 Level 1 (L1) cache is on the processor chip.
 Level 2 (L2) cache is in between main memory
and processor.
 Next level is main memory, implemented as SIMMs.
Much larger, but much slower than cache memory.

Mohan A R, VCET Puttur

Memory Hierarchy:
 Next level is magnetic disks. Huge amount of inexpensive
storage.
 Speed of memory access is critical, the idea is to bring
instructions and data that will be used in the near future as
close to the processor as possible.

Mohan A R, VCET Puttur

Cache Memories:
 The data or contents of the main memory that are used frequently by CPU are stored in the cache
memory so that the processor can easily access that data in a shorter time.
 Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found in
cache memory, then the CPU moves into the main memory.
 Cache memory is placed between the CPU and the main memory.
 The cache is the fastest component in the memory hierarchy and approaches the speed of CPU
components.

Use of a cache memory

Mohan A R, VCET Puttur
Cache Memories:
 When processor issues a Read request, a block of words is transferred from the main memory to the
cache, one word at a time.
 At any given time, only some blocks in the main memory are held in the cache. Which blocks in the
main memory are in the cache is determined by a “mapping function”.
 When the cache is full, and a block of words needs to be transferred from the main memory. Which
block of words in the cache must be replaced is determined by a “replacement algorithm”.

Use of a cache memory

Mohan A R, VCET Puttur
Cache Hit:
 If the CPU wants to read data/instruction or write data into the main memory, the CPU will first check
the entry for that particular data in the cache. If the CPU finds the entry in the cache it is a cache hit.
 Cache hit occurs when,
 The required word is present in the cache memory – Read hit
 The required word is delivered to the CPU from the cache memory – Write hit

Cache Miss:
 If the CPU was not able to find the entry for that particular data in the cache location then it is
a cache miss.
 Cache miss occurs when,
 The required word is not present in the cache memory. The page containing the required word
has to be mapped from the main memory.
Mohan A R, VCET Puttur
Cache Memory Mapping:
 Cache mapping defines how a block from the main memory is mapped to the cache memory in case of
a cache miss.
OR
 Cache mapping is a technique by which the contents of main memory are brought into the cache
memory.

Use of a cache memory

Mohan A R, VCET Puttur
Cache Memory Mapping functions:
 Cache mapping is performed using three different techniques:
i. Direct mapping
ii. Associative mapping
iii. Set-associative mapping.
 Consider a simple processor example
 Cache consisting of 128 blocks of 16 words each
 Total size of cache is 2048 (2K) words
 Main memory is addressable by a 16-bit address
 Main memory has 64K words viewed as 4K blocks of 16
words each.

Mohan A R, VCET Puttur

Direct Mapping:
 A particular block of main memory can map only to a particular line of the cache.

 The line number of cache to which a particular block can map is given by

Cache line number = ( Main Memory Block Address ) Modulo (Number of lines in Cache)
 Consider cache memory is divided into 128 number of lines.
 Block j of the main memory maps onto block j modulo 128 of
the cache. i.e. 0 maps to 0, 129 maps to 1.
 Whenever one of the main memory blocks 0, 128, 256, . . . is
loaded into the cache, it is stored in cache block 0. Blocks 1,
129, 257, . . . are stored in cache block 1, and so on
 Since more than one memory block is mapped onto a given
cache block position, contention may arise for that position
even when the cache is not full.
Mohan A R, VCET Puttur
Direct Mapping:
 Placement of a block in the cache is determined by its memory address.
 Memory address is divided into three fields:

 Word: Low order 4 bits determines one of the 16 words in a

block.
 Block: The 7-bit cache block field determines the cache
position in which this block must be stored.
 Tag: High order 5 bits determines which of the possible 32
blocks is currently present in the cache.
 Simple to implement but not very flexible.

Mohan A R, VCET Puttur

Associative Mapping:
 A block of main memory can map to any line of the cache that is freely available at that
moment.
 This makes fully associative mapping more flexible than direct mapping.

 Memory address is divided into two fields:

 Word: Low order 4 bits determines one of the 16
words in a block.
 Tag: High order 12 bits determines cache position
in which a memory block must be stored.
 The tag bits of an address received from the processor
are compared to the tag bits of each block of the cache
to see if the desired block is present.

Mohan A R, VCET Puttur

Associative Mapping:
 It gives complete freedom in choosing the cache location in which to place the memory
block, resulting in a more efficient use of the space in the cache.
 But the complexity of an associative cache is higher
than that of a direct-mapped cache, because it need to
search all 128 tag patterns to determine whether a
given block is in the cache.
 When a new block is brought into the cache, it replaces
(ejects) an existing block only if the cache is full.
 Replacement algorithm are used to determine which
block has to be replaced
 FCFS (First Come First Serve) Algorithm
 LRU (Least Recently Used) Algorithm
Mohan A R, VCET Puttur
Set-Associative Mapping:
 Set-associative mapping is a combination of direct mapping and associative mapping.
 Blocks of cache are grouped into sets and mapping
function allows a block of the main memory to reside in
any block of a specific set.
 Hence, the contention problem of the direct method is
eased by having a few choices for block placement.
 At the same time, the hardware cost is reduced by
decreasing the size of the associative search.
 Divide the cache into 64 sets, with two blocks per set.
 Memory block 0, 64, 128 etc. map to block 0, and they
can occupy either of the two positions.

Mohan A R, VCET Puttur

Set-Associative Mapping:
 Memory address is divided into three fields:
 Word: Low order 4 bits determines one of the 16
words in a block.
 Set: The 6-bit set field determines the set number.
 Tag: High order 6 bits determines the blocks in a set.
 Number of blocks per set is a design parameter.
 One extreme is to have all the blocks in one set,
requiring no set bits (fully associative mapping).
 Other extreme is to have one block per set, is the same
as direct mapping.

Mohan A R, VCET Puttur

Question Bank:
1. Explain the interfacing of I/O device with computer
2. Illustrate a program that reads one line from the keyboard, stores it in memory buffer, and echoes it back to
the display in an I/O interfaces.
3. Describe the concept of interrupt in computer
4. Explain vectored interrupt
5. Explain interrupt and interrupt hardware, State steps in enabling and disabling interrupts
6. Explain interrupt nesting and handling simultaneous requests in interrupts
7. Describe the parameters – speed size and cost with respect to memory
8. Explain the Direct Memory Access Technique and its importance
9. What is Bus arbitration? Explain different bus arbitration techniques
10. What is cache memory? Analyse the three mapping functions of cache memory

Mohan A R, VCET Puttur