GATE MINIMIZATION

USING BOOLEAN
ALGEBRA

3
 SIMPLIFICATION USING BOOLEAN
ALGEBRA

 Many times in the application of

Boolean algebra, you have to reduce a
particular expression to its simplest
form or change its form to a more
convenient one to implement the
expression most efficiently.

 This approach uses the basic laws,

rules, and theorems of Boolean
algebra to manipulate and simplify an
expression. ECE2003 – DIGITAL LOGIC DESIGN 4
SIMPLIFICATION USING BOOLEAN
ALGEBRA

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SIMPLIFICATION USING BOOLEAN
ALGEBRA

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SIMPLIFICATION USING BOOLEAN
ALGEBRA

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 GATE MINIMIZATION
USING K-MAP METHOD

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 GATE MINIMIZATION USING K-
MAP
SIMPLIFICATION USING KARNAUGH MAP
 The Karnaugh map technique provides
a systematic method for simplifying
and manipulation of Boolean
expressions

 A Karnaugh map is similar to a truth

table because it presents all of the
possible values of input variables and
the resulting output for each value.

 Karnaugh map is an array of cells in

which each cell represents a binary
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 GATE MINIMIZATION USING K-
MAP
SIMPLIFICATION USING KARNAUGH MAP

 The number of cells in a Karnaugh map

is equal to the total number of
possible input variable combinations.

 For n variables on a Karnaugh map

there are 2n numbers of squares. For
three variables, number of cells is 23=
8. For four variables, the number of
cells is 24 = 16.

 Karnaugh maps can be used for

expressions with two, three, four, and 10
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GATE MINIMIZATION USING K-
MAP
SIMPLIFICATION USING KARNAUGH MAP

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 GATE MINIMIZATION USING K-
MAP
3-VARIABLE KARNAUGH MAP
 The 3-variable Karnaugh map is an
array of eight cells.
 In this case, A, B, and C are used for
the variables although other letters
could be used.

 Binary values of A is at the left side

(notice the sequence) and the values
of BC are across the top.

 The value of a given cell is the binary

value of A at the left in the same row 12
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 GATE MINIMIZATION USING K-
MAP
3-VARIABLE KARNAUGH MAP
 Figure shows the standard product
terms that are represented by each
cell in the Karnaugh map.

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 GATE MINIMIZATION USING K-
MAP
4-VARIABLE KARNAUGH MAP
 The 4-variable Karnaugh map is an array of
sixteen cells.

 Binary values of A and B are along the left

side and the values of C and D are across
the top.

 The value of a given cell is the binary

values of A and B at the left in the same
row combined with the binary values of C
and D at the top in the same column.

 For example, the cell in the upper right

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 GATE MINIMIZATION USING K-
MAP
4-VARIABLE KARNAUGH MAP
 Figure shows the standard product
terms that are represented by each
cell in the 4-variable Karnaugh map.

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 GATE MINIMIZATION USING K-
MAP
4-VARIABLE KARNAUGH MAP
 Cells that differ by only one variable are
adjacent & Cells with values that differ by
more than one variable are not adjacent.

 In the 3-variable map the 010 cell is

adjacent to the 000,011 and 110 cell. The
010 cell is not adjacent to the 001, 111,
100, or 101 cell.

 Physically, each cell is adjacent to the

cells that are immediately next to it on
any of its four sides.
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 GATE MINIMIZATION USING K-
MAP
4-VARIABLE KARNAUGH MAP

When we have a difference of 1 bit b/w two

adjacent cells we can easily eliminate
Redundant literals from the expression & then
we can minimize our function which is the
aim of K-Map !

 Why k-map follows gray code logic?

In the case of K-Map, we have difference of only 1-bit b/w adjacent cells.
Consider the case of first 2 cells: 00 01. In case(SOP) if we have 1 in both these
cells then it will produce A'B'+A'B. Which will give A‘. Because B+B'=1.
To utilize this concept of B+B'=1 easily we have Gray code in K-Map.
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 GATE MINIMIZATION USING K-
MAP
GROUPING IN KARNAUGH MAP
 The power of K-maps is in minimizing the
terms, K-maps can be minimized with the
help of grouping the terms to form single
terms.
 When forming groups of squares, observe
the following:
1.Every square containing 1 must be considered
at least once.
2.The number of 1’s in a group must be equal to
2n , i.e. 2,4,8.
3.A group must be as large as possible.
4.A square containing 1 can be included in as
many groups as desired.
5.If a square containing 1 cannot be placed in a
group, then leave it LOGIC
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to include in final 18
 GATE MINIMIZATION USING K-
MAP
TYPES OF GROUPING IN KARNAUGH MAP
 PAIR: Grouping of two 1’s together and
it is represented with three variables

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 GATE MINIMIZATION USING K-
MAP
TYPES OF GROUPING IN KARNAUGH MAP
 QUAD: Grouping of four adjacent 1’s
and it results two variables

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 GATE MINIMIZATION USING K-
MAP
TYPES OF GROUPING IN KARNAUGH MAP
 OCTET: If eight adjacent 1’s are
combined; and represented with by
one variable.

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 GATE MINIMIZATION USING K-
MAP
RULES FOR KARNAUGH MAP MINIMIZATION

1. No zeros allowed in grouping.

2. No diagonals grouping.
3. Only power of 2 number of cells in
each group.
4. Groups should be as large as possible.
5. Every 1’s must be in at least one
group.
6. Overlapping allowed.
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 GATE MINIMIZATION USING K-
MAP
RULES FOR KARNAUGH MAP MINIMIZATION
1. Groups may not include any cell containing a zero

2. Groups may be horizontal or vertical, but not

diagonal

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 GATE MINIMIZATION USING K-
MAP
4. Each group should be as large as possible.

Each cell containing a one must be in at least one group.

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 GATE MINIMIZATION USING K-
MAP
6. Groups may overlap.

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 GATE MINIMIZATION USING K-
MAP
7. Groups may wrap around the table. The leftmost
cell in a row may be grouped with the rightmost
cell and the top cell in a column may be grouped
with the bottom cell.

8. There should be as few groups as possible, as long

as this does not contradict any of the previous rules.

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 GATE MINIMIZATION USING K-
MAP
PROCEDURE FOR K- MAP SOP MINIMIZATION

The generalized procedure to simplify Boolean

expressions as follows:
1.Plot the K-map and place 1’s in those cells
corresponding to the 1’s in the sum of product
expression. Place 0’s in the other cells.
2.Check the K-map for adjacent 1’s and encircle those
1’s which are not adjacent to any other 1’s. These
are called isolated 1’s.
3.Check for those 1’s which are adjacent to only one
other 1 and encircle such pairs.
4.Check for quads and octets of adjacent 1’s even if it
contains some 1’s that have already been encircled.
While doing this make sure that there are minimum
number of groups.
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GATE MINIMIZATION USING K-
MAP
3-Variable K-Maps Simplification

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GATE MINIMIZATION USING K-
MAP
3-Variable K-Maps Simplification

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 GATE MINIMIZATION USING K-
MAP
K- MAP SOP MINIMIZATION

Design an car driver alert system based

on following condition. The buzzer (B=1)
will alert the driver whenever any one of
the following condition is satisfied.

(i). When engine is ON (E=1) and any one

of the door is opened (D=1)
(ii).when fuel level is low (F=1)
(iii). When car exceed speed limit (S=1)

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GATE MINIMIZATION USING K-
MAP
PROCEDURE FOR K- MAP SOP MINIMIZATION

Truth table

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GATE MINIMIZATION USING K-
MAP
PROCEDURE FOR K- MAP SOP MINIMIZATION

K-MAP

B=F+S+ED

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T CARES

 A don’t care minterm is a combination

of variables whose logical value is not
specified.

 When choosing adjacent squares to

simplify the function in a map, the
don’t care minterm may be assumed to
be either 0 or 1.

 When simplifying the function, we can

choose to include each don’t care
minterm with either the 1’s or the 0’s, 37
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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T CARES

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T CARES

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS
 For a POS expression in standard form,
a 0 is placed on the Karnaugh map for
each sum term in the expression & the
cells that do not have a 0 are the cells
for which the expression is 1.

 Steps for the POS K-mapping process.

Step 1: Determine the binary value of each
sum term in the standard POS expression.
This is the binary value that makes the term
equal to 0.
Step 2: As each sum term is evaluated, place
a 0 on the Karnaugh map in the 40
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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS - EXAMPLE

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS
 Reduce F(W,X,Y,Z) = ∏(0,1,2,4,5,7,10,15)
using K-map

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GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS

F = (W+Y) . (X’+Y’+Z’) . (X+Y’+Z)

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 GATE MINIMIZATION USING K-
MAP
K-MAP SIMPLIFICATION OF POS FORMS
 Use a Karnaugh map to minimize the
following POS expression:
(B+ C+D)(A+B+C’+D)(A’+B+C+D’)(A+B’+C+D)(A’+B’+
C+D)

The first term must be

expanded into A’ + B + C + D
and A + B + C + D to get a
standard POS expression,
which is then mapped;

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 GATE MINIMIZATION USING K-
MAP
KARNAUGH MAP MINIMIZATION - EXERCISE
Using a Karnaugh map, simplify the following functions and
implement them with basic gates.
(a) F (A, B, C, D) = Σm (0, 2, 3, 6, 7, 8, 10, 11, 12, 15)
(b) F (A, B, C, D) = Σm (0, 2, 3, 5, 7, 8, 13) + d (1, 6,
12)
(c) F (A, B, C, D) = Σm (1, 7, 9, 10, 12, 13, 14, 15) + d (4, 5, 8)
(d) F (A, B, C, D) = πM (0, 8, 10, 11, 14) + d (6)
(e) F (A, B, C, D) = π M(2, 8, 11, 15) + d (3, 12, 14)
(f) F (W, X, Y, Z) = πM (0, 2, 6, 11, 13, 15) + d (1, 9, 10,
14)
Prepare a Karnaugh map for the following functions.
(a) F = ABC + A'BC + B'C'
(b) F = A + B + C'
(c) Y = AB + B'CD
Using the Karnaugh map method, simplify the following
functions, obtain their sum of the products form, and product
of the sums form. Realize them with basic gates.
(a) F (W, X, Y, Z) = Σ (1, 3, 4, 5, 6, 7, 9, 12, 13)
(b) F (W, X, Y, Z) = Σ (1, 5, 6, 7, 11, 12, 13, 15)
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 NAND & NOR
IMPLEMENTATION

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 NAND & NOR
IMPLEMENTATION
UNIVERSAL LOGIC GATES
 OR, AND and NOT gates are the three
basic logic gates as they together can be
used to construct the logic circuit for any
given Boolean expression.

 The combination of NAND gates or a

combination of NOR gates can be used to
perform functions of any of the basic
logic gates.

 And also, NAND and NOR gates are

referred to as universal gates because
each alone can be combined together 48
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 NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC GATE
 The NAND gate is a universal gate because it
can be used to produce any of the other logic
gates function.

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 NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC GATE

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 NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC GATE

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 NAND & NOR
IMPLEMENTATION
NOR GATE AS UNIVERSAL LOGIC GATE
 Like the NAND gate, the NOR gate can
be used to produce any logic function.

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 NAND & NOR
IMPLEMENTATION
NOR GATE AS UNIVERSAL LOGIC GATE

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 NAND & NOR
IMPLEMENTATION
NOR GATE AS UNIVERSAL LOGIC GATE

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 NAND & NOR
IMPLEMENTATION
NAND & NOR IMPLEMETATION

 Digital circuits are more frequently

constructed using NAND and NOR
gates than with AND and OR gates

 NAND and NOR gates are easier to

fabricated with other electronics
components and these are the basic
gates used in most digital logic IC
families

 To ease the conversion of NAND, NOR

logic it is convenient to define other 55
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 NAND & NOR
IMPLEMENTATION
NAND & NOR IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

 Implement the following logical

expression into an equivalent NAND
gate based logic circuit
F= AB + CD + E

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

AND is gate is replaced by NAND gate

and OR gate is replaced by NAND gate
with inverted OR gate
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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION - EXAMPLES

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION - EXAMPLES

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 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION - EXAMPLES

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION
 NOR function is a dual of NAND function,
so all procedures and rules followed for
NOR will be dual of NAND logic realization

 Implementation of boolean function with

G
NOR gates requires that the function to
be simplified in POS forms
 The POS specifies a group of OR gates
for the sum terms, followed by AND gates
to produce the product

 So, it transfers the OR-AND logic circuits

into the NOR-NOR logic circuits. 66
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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other Examples

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