Error Control
Error Control
Error Detection
and
Correction
10.1 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Note
10.2
10-1 INTRODUCTION
10.3
Note
10.4
Figure 10.1 Single-bit error
10.5
Note
10.6
Figure 10.2 Burst error of length 8
10.7
Note
10.8
Figure 10.3 The structure of encoder and decoder
10.9
10-2 BLOCK CODING
10.10
Figure 10.5 Datawords and codewords in block coding
10.11
Error detection in block coding
10.12
Example 10.2
Dataword – 01
Codeword - 011
10.15
Error correction
10.16
Error correction
• More redundant bits added to correct an error without knowing
what was actually sent.
• 3 redundant bits are added to the 2-bit dataword to make 5-bit
codewords. Table below shows the datawords and codewords.
Assume the dataword is 01.
10.17
Example 10.3 (continued)
1. Comparing the received codeword (01001) with the first codeword
(00000) in the table, the receiver decides that the first codeword is not
the one that was sent because there are two different bits.
3. The original codeword must be the second one in the table because this
is the only one that differs from the received codeword by 1 bit. The
receiver replaces 01001 with 01011 and consults the table to find the
dataword 01.
10.18
Note
10.19
Example 10.4
10.20
Note
10.21
Example 10.5
Solution
We first find all Hamming distances.
Solution
We first find all the Hamming distances.
10.24
10-3 LINEAR BLOCK CODES
10.25
Note
10.26
Example 10.10
10.27
Simple parity check code
• Dataword – k bits
• Codeword – n bits (n = k + 1), extra bit called the parity bit.
• Parity bit used to make the total number of 1’s in the
codeword even.
• Min. Hamming dist. (dmin) = 2, useful for detecting single bit
error.
10.28
Encoder and decoder for simple parity-check code
10.29
Working principle of simple parity-check code
• Calculation done in modular arithmetic.
Sender side
• Generator takes a copy of 4-bit dataword and generates parity bit (r 0)
r0 = a3 + a2 + a1 + a0 (modulo 2)
• Codeword (5 bits) – dataword (4 bits) + parity bit (1 bit)
• Parity bit makes the total number of 1’s is the codeword even.
10.30
Working principle of simple parity-check code
Receiver side
•Checker performs the same operation on 5-bit codeword to
generate the syndrome (s0)
s0 = b3 + b2 + b1 + b0 + q0 (modulo 2)
10.31
Example
Sender
Dataword – 1011 -------> Codeword - 10111
Five cases:
1. No error occurs; the received codeword is 10111. The
syndrome is 0. The dataword 1011 is created.
2. One single-bit error changes a1 . The received
codeword is 10011. The syndrome is 1. No dataword
is created.
3. One single-bit error changes r0 . The received codeword
is 10110. The syndrome is 1. No dataword is created.
10.32
Example 10.12 (continued)
10.33
Note
10.34
10-4 CYCLIC CODES
1 0 1 1 0 0 0
Cyclic shift
0 1 1 0 0 0 1
10.35
Table 10.6 A CRC code with C(7, 4)
10.36
Cyclic Redundancy Check (CRC) encoder and decoder
10.37
Cyclic Redundancy Check (CRC)
Sender side
•Dataword – k bits Codeword – n bits
•To generate codeword
• (n – k) 0s are appended to the dataword.
• It is fed to a generator, which uses a divisor of size (n – k + 1),
which is agreed upon.
• Generator divides the augmented dataword (modulo 2 division) –
quotient discarded, remainder appended to the dataword
10.38
Cyclic Redundancy Check (CRC)
Receiver side
•Received codeword fed to the checker, which performs modulo 2
division on n bits.
•Output is called syndrome of (n – k) bits, this is fed to the decision
logic analyzer.
• If all bits are 0s, the first k bits are accepted as dataword.
• Otherwise, the k bits are discarded.
10.39
Sender side: Division in CRC encoder
10.40
Receiver side: Division in the CRC decoder for two cases
10.41