Chapter 4: Modules and Ports

Lecture 14: [HDL Based system Design]

by
Dr. Rita Mahajan
Learning Objectives
• Components of a Verilog module definition
• Port list for a module and declare it in Verilog.
• Port connection rules in a module instantiation.
• Understand how to connect ports to external signals, by ordered
list, and by name.
• Explain hierarchical name referencing of Verilog identifiers.
 MODULES
 A module in Verilog consists of distinct parts, as shown in Figure below.
 Contd..
 A module definition always begins with the keyword module. The module name,
port list, port declarations, and optional parameters must come first in a module
definition.
 Port list and port declarations are present only if the module has any ports to
interact with the external environment.
 The five components: variable declarations, dataflow statements, instantiation of
lower modules, behavioral blocks, and tasks or functions.
 These components can be in any order and at any place in the module definition.
 The endmodule statement must always come last in a module definition.
 All components except module, module name, and endmodule are optional.
 Verilog allows multiple modules to be defined in a single file. The modules can
be defined in any order in the file.
 Example of S-R latch

 The SR latch has S and R as the input ports and Q and Qbar as the output ports.
 S-R latch Module
// Module name and port list
// SR_latch module
module SR_latch(Q, Qbar, Sbar, Rbar);
//Port declarations
output Q, Qbar;
input Sbar, Rbar;
// Instantiate lower-level modules
// In this case, instantiate Verilog primitive nand gates
// Note, how the wires are connected in a cross-coupled fashion.
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
// endmodule statement
endmodule
 .
• Primitive instances
Verilog has several built-in primitives that model gates and switches.

The built-in primitives can be instanced in modules to create a structural description of the
module’.

Verilog has the following built-in primitives:

 S-R latch Stimulus Module
• module Top;
• wire q, qbar;
• reg set, reset;
• SR_latch m1(q, qbar, ~set, ~reset);
• initial
• begin
• $monitor($time, " set = %b, reset= %b, q= %b\n", set, reset, q);
• set = 0; reset = 0;
• #5 reset = 1;
• #5 reset = 0;
• #5 set = 1;
• End
• endmodule
 PORTS
 Ports provide the interface by which a module can communicate with its
environment. For example, the input/output pins of an IC chip are its ports.
 The environment can interact with the module only through its ports.
 The internals of the module are not visible to the environment. This provides a
very powerful flexibility to the designer.
 Ports are also referred to as terminals.
 LIST OF PORTS
 A module definition contains an optional list of ports. If the module does not
exchange any signals with the environment, there are no ports in the list.
 Consider a 4-bit full adder that is instantiated inside a top-level module Top. The
diagram for the input/output ports is shown in Figure below.

 The module Top is a top-level module. The module fulladd4 is instantiated

below Top. The module fulladd4 takes input on ports a, b, and c_in and
 Contd…

 Thus, module fulladd4 performs an addition for its environment. The module Top is
a top-level module in the simulation and does not need to pass signals to or receive
signals from the environment.
 Thus, it does not have a list of ports. The module names and port lists for both
module declarations in Verilog are as shown below.

• module fulladd4(sum, c_out, a, b, c_in); //Module with a list of ports

• module Top; // No list of ports, top-level module in simulation
 PORT DECLARATION
 All ports in the list of ports must be declared in the module.
 Ports can be declared by keywords: input, output and inout
 Each port in the port list is defined as input, output, or inout, based on the direction
of the port signal. Example of the fulladd4:
• module fulladd4(sum, c_out, a, b, c_in);
• //Begin port declarations section
• output[3:0] sum;
• output c_cout;
• input [3:0] a, b;
• input c_in;
• //End port declarations section
<module internals>
• endmodule
 Contd…
 All port declarations are implicitly declared as wire in Verilog. Thus, if a port is
intended to be a wire, it is sufficient to declare it as output, input, or inout. Input or
inout ports are normally declared as wires.
 If output ports hold their value, they must be declared as reg, e.g. for DFF, we
wanted the output q to retain its value until the next clock edge.
module DFF(q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
endmodule
 Ports of the type input and inout cannot be declared as reg because reg variables
store values and input ports should not store values but simply reflect the changes in
the external signals they are connected to.
 Contd…
 Module fulladd4 can be declared using an ANSI C style syntax to specify the ports
of that module. Each declared port provides the complete information about the
port.
 ANSI C style port declaration syntax is shown below.
module fulladd4(output reg [3:0] sum,
output reg c_out,
input [3:0] a, b, //wire by default
input c_in); //wire by default
...
<module internals>
endmodule
 This syntax avoids the duplication of naming the ports in both the module definition
statement and the module port list definitions.
 If a port is declared but no data type is specified, then, under specific circumstances,
 PORT CONNECTION RULES
 One can visualize a port as consisting of two units, one unit that is internal to the
module and another that is external to the module.
 The internal and external units are connected. There are rules governing port
connections when modules are instantiated within other modules. The Verilog
simulator complains if any port connection rules are violated.
 These rules are summarized in given Figure.
 Contd…
 Inputs: Internally, input ports must always be of the type net. Externally, the inputs
can be connected to a variable which is a reg or a net.
 Outputs: Internally, outputs ports can be of the type reg or net. Externally, outputs
must always be connected to a net. They cannot be connected to a reg.
 Inouts: Internally, inout ports must always be of the type net. Externally, inout ports
must always be connected to a net.
 Width matching: It is legal to connect internal and external items of different sizes
when making intermodule port connections. However, a warning is typically issued
that the widths do not match.
 Unconnected ports: Verilog allows ports to remain unconnected. For example,
certain output ports might be simply for debugging, and you might not be interested
in connecting them to the external signals.
 You can let a port remain unconnected by instantiating a module as shown below.
fulladd4 fa0(SUM, , A, B, C_IN); // Output port c_out is unconnected
 EXAMPLE OF ILLEGAL PORT CONNECTION
• To illustrate port connection rules, assume that the example of module fulladd4 is
instantiated in the stimulus block Top. Given example shows an illegal port
connection.
module Top;
reg [3:0] A,B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;
fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
//Illegal connection because output port sum in module fulladd4
//is connected to a register variable SUM in module Top.
.<stimulus>
Endmodule
 This problem is rectified if the variable SUM is declared as a net (wire).
 CONNECTING PORTS TO EXTERNAL SIGNALS
 There are two methods of making connections between signals specified in the
module instantiation and the ports in a module definition.
 Connecting by ordered list
The signals to be connected must appear in the module instantiation in the same order
as the ports in the port list in the module definition. To connect signals in module Top
by ordered list, the Verilog code is shown below.

Notice that the external signals SUM, C_OUT, A, B, and C_IN appear in exactly the
 Contd..
Connecting ports by name
 For large designs where modules have, say, 50 ports, remembering the order of the
ports in the module definition is impractical and error-prone.
 Verilog provides the capability to connect external signals to ports by the port
names, rather than by position.
 We could connect the ports by name for full adder example by instantiating the
module fulladd4, as follows.
 Contd..
Connecting ports by name
 Note that only those ports that are to be connected to external signals must be
specified in port connection by name.
 Unconnected ports can be dropped. For example, if the port c_out were to be kept
unconnected, the instantiation of fulladd4 would look as follows. The port c_out is
simply dropped from the port list.

 Another advantage of connecting ports by name is that as long as the port name is
not changed, the order of ports in the port list of a module can be rearranged without
changing the port connections in module instantiations.
 HIERARCHICAL NAMES
 Verilog supports a hierarchical design methodology. Every module instance, signal,
or variable is defined with an identifier.
 A particular identifier has a unique place in the design hierarchy. Hierarchical name
referencing allows us to denote every identifier in the design hierarchy with a
unique name.
 A hierarchical name is a list of identifiers separated by dots (".") for each level of
hierarchy. Thus, any identifier can be addressed from any place in the design by
simply specifying the complete hierarchical name of that identifier.
 The top-level module is called the root module because it is not instantiated
anywhere. It is the starting point. To assign a unique name to an identifier, start from
the top-level module and trace the path along the design hierarchy to the desired
identifier.
 Contd…
 To clarify this process, the design hierarchy for simulation of SR latch is shown.
 Contd…
 For this simulation, stimulus is the top-level module. Since the top-level module is
not instantiated anywhere, it is called the root module.
 The identifiers defined in this module are q, qbar, set, and reset. The root module
instantiates m1, which is a module of type SR_latch. The module m1 instantiates
nand gates n1 and n2.
 Q, Qbar, S, and R are port signals in instance m1. Hierarchical name referencing
assigns a unique name to each identifier. To assign hierarchical names, use the
module name for root module and instance names for all module instances below
the root module.
 Contd…
 Given example shows hierarchical names for all identifiers in the above simulation.
Notice that there is a dot (.) for each level of hierarchy from the root module to the
desired identifier.

 Each identifier in the design is uniquely specified by its hierarchical path name. To
display the level of hierarchy, use the special character %m in the $display task.