RISC V Architecture

Vanamala H R
Department of Electronics and
Communication Engg.
 RISC V
ARCHITECTURE

UNIT 3: Instructions: The Language of Computer

Vanamala H R
Department of Electronics and Communication Engineering
RISC V Instruction Set Architecture (ISA)
Operands of the Computer Hardware
RISC V Registers

 Registers can be used either name (i.e., ra,

zero) or x0, x1, etc. Using name is preferred
 Registers used for specific purposes:
 zero always holds the constant value 0.
 the saved registers, s0-s11, used to hold
variables
 the temporary registers, t0-t6, used to
hold intermediate values during a larger
computation
 Function arguments / return
values
 Pointers – Stack, Global, Thread

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Representing Instructions in the Computer
RISC-V – It’s Instruction Format

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Supporting Procedures in Computer Hardware

What is and what is not preserved across a procedure call

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Slti: set on less than

Sltiu: set on less than unsigned

slt and sltu compare two registers as signed and unsigned numbers,
respectively, then write 1 to a register if the first value is less than the second
value, or 0 otherwise. slti and sltiu perform the same comparisons, but with
an immediate for the second operand.

slti and sltiu perform the same comparisons, but with an immediate for the
second operand.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Heap memory:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Illustration of four RISC-V addressing modes

Addressing in Branches

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Supporting Procedures in Computer Hardware

RISC-V register conventions for assembly language.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
 RISC V
ARCHITECTURE

UNIT 3: Instructions: The Language of Computer

Vanamala H R
Department of Electronics and Communication Engineering
 RISC V Instruction Set Architecture (ISA)

Parallel Execution—Cooperation is required-Synchronization ----- else leads

to Data Race condition
Cooperation usually means some tasks are writing new values that
others must read. To know when a task is finished writing so that it is safe for
another to read, the tasks need to synchronize
In computing, synchronization mechanisms are typically built with user-level
software routines that rely on hardware-supplied synchronization
instructions --Lock and Unlock procedures used
One such hardware primitive and show how it can be used to build a basic
synchronization primitive- atomic exchange or atomic swap –interchanges a
value in a register for a value in memory.
Used in atomic compare and swap or atomic fetch-and-increment
Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
 RISC V Instruction Set Architecture (ISA)

Complex atomic memory operations on a single memory word are performed

with the load-reserved (LR) and store-conditional (SC) instructions.

LR loads a word from the address in rs1, places the sign-extended value in rd,
and registers a reservation on the memory address.

SC writes a word in rs2 to the address in rs1, provided a valid reservation still
exists on that address. SC writes zero to rd on success or a nonzero code on
failure.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

The program next acquires a lock at the location in register x20, where the
value of 0 means the lock was free and 1 to mean lock was acquired:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Assembler- pseudoinstructions :

li x9, 123 // load immediate value 123 into register x9

addi x9, x0, 123 // register x9 gets register x0 + 123

li x9,0x8123
lui x9 0x8
addi x9 x9 291

la x10,num
auipc x10 0x10000
addi x10 x10 0
Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Assembler- pseudoinstructions :

mv x10, x11 // register x10 gets register x11

addi x10, x11, 0 // register x10 gets register x11 + 0

and x9, x10, 15 // register x9 gets x10 AND 15

andi x9, x10, 15 // register x9 gets x10 AND 15

j Label //unconditionally branch to a label

jal x0, Label //unconditionally branch to a label

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

li x9, 123 // load immediate value 123 into register x9

addi x9, x0, 123 // register x9 gets register x0 + 123

mv x10, x11 // register x10 gets register x11

addi x10, x11, 0 // register x10 gets register x11 + 0

The hardware need not implement these instructions; however, their

appearance in assembly language simplifies translation and programming.
Such instructions are called pseudoinstructions.

j Label to unconditionally branch to a label, as a stand-in for jal x0, Label

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

A translation hierarchy for C:

UNIX follows a suffix convention for files: C source files are named
x.c, assembly files are x.s, object files are named x.o, statically linked
library routines are x.a, dynamically linked library routes are x.so,
and executable files by default are called a.out.

MS-DOS uses the suffixes .C, .ASM, .OBJ, .LIB, .DLL, and .EXE to the
same effect.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
 RISC V Instruction Set Architecture (ISA)
Producing an object file:

Assembler (or compiler) translates program into machine instructions

•Provides information for building a complete program. The object file for UNIX
systems typically contains six distinct pieces:
•Header: described contents of object module
•Text segment: translated instructions- contains the machine language code.
•Static data segment: data allocated for the life of the program
•Relocation info: for contents that depend on absolute location of loaded program
Symbol table: global definitions and external refs : A table that matches names of
labels to the addresses of the memory words that instructions occupy
•Debug info: for associating with source code- contains a concise description of
how the modules were compiled so that a debugger can associate machine
instructions with C source files and make data structures readable.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
 RISC V Instruction Set Architecture (ISA)

Linking Object Modules :

Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3.Patch location-dependent and external refs.

(Typically, this file has the same format as an object file, except that it contains
no unresolved references. It is possible to have partially linked files, such as
library routines, that still have unresolved addresses and hence result in object
files.)
•Could leave location dependencies for fixing by a relocating loader
•When the linker places a module in memory, all absolute references, that is,
memory addresses that are not relative to a register, must be relocated to
reflect its true location
Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

The RISC-V memory allocation for program and data :

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
 RISC V Instruction Set Architecture (ISA)
Loading a Program:

The loader follows these steps in UNIX systems:

1.Reads the executable file header to determine size of the text and data segments.
2.Creates an address space large enough for the text and data.
3.Copies the instructions and data from the executable file into memory.
4.Copies the parameters (if any) to the main program onto the stack.
5.Initializes the processor registers and sets the stack pointer to the first free location.
6.Branches to a start-up routine that copies the parameters into the argument registers
and calls the main routine of the program. When the main routine returns, the start-up
routine terminates the program with an exit system call

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
Dynamic Linking:

Only link/load library procedure when it is called

•Requires procedure code to be relocatable
•Avoids image bloat caused by static linking of all (transitively) referenced
libraries
•Automatically picks up new library versions

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)
RISC-V assembly version of procedure sort :

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

C sort Program:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Procedure to swap:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Sort Procedure in C:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

The outer Loop:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Inner Loop:

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

2.35 Consider the following code:

lb x6, 0(x7)
sw x6, 8(x7)

Assume that the register x7 contains the address 0×10000000 and

the data at address is 0×1122334455667788.

2.35.1 [5] <§2.3, 2.9> What value is stored in 0×10000008 on a big-endian

machine?
2.35.2 [5] <§2.3, 2.9> What value is stored in 0×10000008 on a little-endian
machine?

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
2.35.1 0x11
2.35.2 0x88
RISC V Instruction Set Architecture (ISA)

2.36 [5] <§2.10> Write the RISC-V assembly code that creates the 32-bit
constant 0x12345678hex and stores that value to register x10.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V Instruction Set Architecture (ISA)

2.36 [5] <§2.10> Write the RISC-V assembly code that creates the 32-bit
constant 0x12345678hex and stores that value to register x10.

2.37 [10] <§2.11> Write the RISC-V assembly code to implement the following
C code as an atomic “set max” operation using the lr.d/sc.d instructions. Here,
the argument shvar contains the address of a shared variable which should be
replaced by x if x is greater than the value it points to:
void setmax(int* shvar, int x) {
// Begin critical section
if (x > *shvar)
*shvar = x;
// End critical section}
Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
}
RISC V Instruction Set Architecture (ISA)

2.38 [5] <§2.11> Using your code from Exercise 2.37 as an example, explain
what happens when two processors begin to execute this critical section at the
same time, assuming that each processor executes exactly one instruction per
cycle.

Reference : Computer Architecture with RISC V - The Hardware/Software Interface: RISC-V Edition by David A. Patterson and John L. Hennessy
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set

RISC V Additional Instructions of Base Architecture

To make an instruction set architecture suitable for a wide variety of

computers, the RISC-V architects partitioned the instruction set into a
base architecture and several extensions
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
AUIPC (Add Upper Immediate to PC)

(AUIPC) adds the 20-bit immediate value to the upper 20 bits of the program
counter (pc) and stores the result in the destination register (rd).

AUIPC forms a 32-bit temporary offset, by adding the 20-bit immediate value to
the upper 20 bits of temporary offset, filling in the lower 12 bits with zeros.

The temporary offset is added to the pc, to form the pc-relative address. The
result is placed in the destination register (rd).
Syntax

where, rd destination register

auipc rd, imm imm immediate value
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
Instruction Format

Opcode
Example:

Assuming pc is at 0x800000ff.
auipc x5, 0x00110
imm = 0x00110
x5 ←− 0x00110000 + 0x800000ff
A.E X5= e 0x801100ff.
RISC V ARCHITECTURE
The Rest of the RISC-V
Instruction Set
SLT(Set Less Than)

Syntax
slt rd, rs1, rs2

Performs the signed comparison between (rs1) and

(rs2) if rs1 < rs2,
rd=1
else rd=0
Example:
li x5, 3 # x5 ←− 3
li x3, 5 # x3 ←−
slt x1, x5, x3 5 x1 will have a value 1.
# x1 ←−
x5 < x3
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
SLTU (Set Less Than Unsigned)
Syntax
sltu rd, rs1, rs2

Description:Performs the unsigned comparison between (rs1) and

(rs2)
if rs1 < rs2,
rd=1
else rd=0
li x5, 0x80000000
Example:1 # x5 ←− 0x80000000
li x3, 0xffffffff # x3 ←− 0xffffffff
slt x1, x5, x3 # x1 ←− x5 < x3 x1 will have a value 1.

2) SLTU rd, x0, rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
SLTI (Set Less than Immediate)

Syntax
slti rd, rs1, imm

Description :A SLTI performs signed comparison of contents of register (rs1) and

Immediate data (imm). If the value in register is less than the immediate value, value 1
is stored in destination register, otherwise, value 0 is stored in the destination register.

Example: slti x5, x1, 2

x5=1 if x1<2
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
SLTIU (Set Less Than Immediate Unsigned )

Syntax
sltiu rd, rs1, imm

Description:does unsigned comparison between register contents (rs1) and Immediate

data (imm).
If the value in register is less than the immediate value, the value 1 is stored in
destination Register, otherwise, the value 0 is stored in destination register.

Example: sltiu x5, x1, 2 x5=0 if x1=0xf0000000

sltiu rd, rs1, 1 sets rd to 1 if rs1 equals zero, otherwise sets rd to 0

RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set

Example:
For general signed addition, overflow checking requires three additional
instructions after the addition to identify that the sum should be less than one of
the operands if and only if the other operand is negative.

add t0, t1, t2

slti t3, t2, 0
slt t4, t0, t1
bne t3, t4,
overflow
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set

RISC V Extensions

The first, M, adds instructions to multiply and divide integers.

Next unit will introduce several instructions in the M extension.
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
RISC V Extensions Contd
The second extension, A, supports atomic memory operations for
multiprocessor synchronization.

The load-reserved (lr.w) and store-conditional (sc.w) instructions

introduced earlier are members of the A extension.

The remaining 18 instructions are optimizations of common

synchronization patterns, like atomic exchange and atomic addition.

The third and fourth extensions, F and D, provide operations on floating-

point numbers, which are described in next unit
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set

RISC V Extensions Contd

The last extension, C, provides no new functionality at all. Rather, it takes

the most popular RISC-V instructions, like addi, and provides equivalent
instructions that are only 16 bits in length, rather than 32.

It thereby allows programs to be expressed in fewer bytes, which can

reduce cost.

To fit in 16 bits, the new instructions have restrictions on their operands:

for example, some instructions can only access some of the 32 registers,
and the immediate fields are narrower.
RISC V ARCHITECTURE
Arrays versus Pointers

Array indexing involves

Multiplying index by element size
Adding to array base address

Pointers correspond directly to memory addresses

Can avoid indexing complexity

Comparing assembly code that uses arrays and array indices to the
assembly code that uses pointers offers insights about pointers.

Examples below show how pointers map into RISC-V

instructions,
RISC V ARCHITECTURE

Arrays versus Pointers:

Example: Clearing an Array

C Code

clear1(int array[], int size) {

int i;
for (i = 0; i < size; i += 1)
array[i] = 0;
}

Let the two

parameters array
is mapped to
x10
RISC V ARCHITECTURE
Arrays versus Pointers
Example: Clearing an Array

Assembly code
li // i = 0
loop1: slli x6, x5 ,2 // x6 = i * 4
x5,0
add x7, x10, x6 // x7 = address of
array[i] sw x0, 0(x7) // array[i] = 0
addi x5, x5, 1 // i = i + 1
blt x5,x11,loop1 // if (i<size) go
to loop1
RISC V ARCHITECTURE
Arrays versus Pointers

Pointer Version of Clear

clear2(int*array, int size) {
int *p;
for (p = &array[0]; p < &array[size];
p = p + 1)
*p = 0;
}

Let the two parameters array is mapped to x10

size is mapped to x11,
and p is allocated to register
x5
RISC V ARCHITECTURE
Arrays versus Pointers
Pointer Version of Clear
Assembly code

mv x5,x10 // p = address of array[0]

OR
add x5,x10,x0
slli x6,x11,2 // x6 = size * 4
add x7,x10,x6 // x7 = address of array[size]

loop2:
sw x0,0(x5) // Memory[p] = 0
addi x5,x5,4 // p = p + 4
bltu x5,x7,loop2 // if (p<&array[size]) go to loop2
RISC V ARCHITECTURE
Arrays versus Pointers
Pointer Version of Clear
Assembly code
RISC V ARCHITECTURE
Arrays versus Pointers
Pointer Version of Clear
Assembly code: xly and add outside the loop:
RISC V ARCHITECTURE
Arrays versus Pointers

• In Array version “multiply” and add inside the loop because i is incremented and
each address must be recalculated from the new index.

• The memory pointer version increments the pointer p directly.

• The pointer version moves the scaling shift and the array bound addition outside the
loop,
thereby reducing the instructions executed per iteration from five to three.

• Compiler can achieve same effect as manual use of pointers

 strength reduction (shift instead of multiply)
 induction variable elimination (eliminating array address calculations within
loops).
RISC V ARCHITECTURE
Instructions: The Language of Computer –Part-B

Rajeshwari B
Department of Electronics and Communication Engineering
RISC V ARCHITECTURE
Compiling C

Structure of recent compilers

RISC V ARCHITECTURE
Compiling C

Example:
To illustrate the concepts, the C version of a while loop considered

while (save[i] == k)
i += 1;

The Front End

The function of the front end is to read in a source program; check the
syntax and semantics;

translate the source program to an intermediate form that interprets

most of the language-specific operation of the program.
RISC V ARCHITECTURE
Compiling C
The front end is typically broken into four separate functions:

1. Scanning reads in individual characters and creates a string of tokens. Examples

of tokens are reserved words, names, operators, and punctuation symbols.

In the above example, the token sequence is while, (, save, [, i, ], ==, k, ), i, +=, 1.

A word like while is recognized as a reserved word in C, but save, i, and j are
recognized as names, and 1 is recognized as a number.

2. Parsing takes the token stream, ensures the syntax is correct, and produces an
abstract syntax tree, which is a representation of the syntactic structure of the
program.
RISC V ARCHITECTURE
Compiling C

3. Semantic analysis takes the abstract syntax tree and checks the program
for semantic correctness. Semantic checks normally ensure that variables
and types are properly declared and that the types of operators and objects
match, a step called type checking.

During this process, a symbol table representing all the named objects—
classes, variables, and functions—is usually created and used to type-check
the program.

4. Generation of the intermediate representation (IR) takes the symbol table

and the abstract syntax tree and generates the intermediate representation
that is the output of the front end.

The most common intermediate form looks much like the RISC-V instruction
set but with an infinite number of virtual registers;
RISC V ARCHITECTURE
Compiling C

High-Level Optimizations

High-level optimizations are transformations that are done at source level

The most common high-level transformation is probably procedure inlining,

which replaces a call to a function by the body of the function, substituting
the caller’s arguments for the procedure’s parameters.

Loop transformations that can reduce loop overhead,-Loop-unrolling

involves taking a loop, replicating the body multiple times, and executing
the transformed loop fewer times.
RISC V ARCHITECTURE
Compiling C
Local and Global Optimizations

Three classes of optimization are performed:

1. Local optimization works within a single basic block. A local optimization pass is
often run as a precursor and successor to global optimization to “clean up” the
code before and after global optimization.

2. Global optimization works across multiple basic blocks;

3. Global register allocation allocates variables to registers for regions of the code.
Register allocation is crucial to getting good performance in modern processors.
RISC V ARCHITECTURE
Compiling C

Example: Optimization- Common sub expression elimination

multiple instances of the same expression and replaces the second one by a
reference to the first. Consider, for example, a code segment to add 4 to an
array element: x[i] = x[i] + 4
Recalculating address x[i] again using
different set of registers
x[i] = x[i] + 4
// x[i] + 4

sw r105,0(r109)
lw r104, 0(r103)
addi r105, r104,4
RISC V ARCHITECTURE
Compiling C
Common subexpression elimination
// x[i] + 4

addi r100, x0, x

lw r101,I
slli r102,r101,2 // Strength reduction Replacing mul with shift
add r103,r100,r102
lw r104, 0(r103)

addi r105, r104,4

sw r105, 0(r103) // value of x[i] is in r104
RISC V ARCHITECTURE
Compiling C
Other optimizations:

■ Strength reduction replaces complex operations by simpler ones and can be applied
to this code segment, replacing the mul by a shift left.

■ Constant propagation and its sibling constant folding find constants in code and
propagate them, collapsing constant values whenever possible.

■ Copy propagation propagates values that are simple copies, eliminating the need to
reload values and possibly enabling other optimizations, such as common
subexpression elimination.

■ Dead store elimination finds stores to values that are not used again and eliminates
the store; its “cousin” is dead code elimination, which finds unused code—code that
cannot affect the result of the program—and eliminates it.
RISC V ARCHITECTURE
Compiling C

Global Code Optimizations

Many global code optimizations have the same aims as those used in the local case,
including common subexpression elimination, constant propagation, copy
propagation, and dead store and dead code elimination.

There are two other important global optimizations: code motion and induction
variable elimination. Both are loop optimizations; that is, they are aimed at code in
loops.

Code motion finds code that is loop invariant: a particular piece of code computes
the same value on every iteration of the loop and, hence, may be computed once
outside the loop.
Induction variable elimination is a combination of transformations that reduce
overhead on indexing arrays, essentially replacing array indexing with pointer
accesses.
RISC V ARCHITECTURE
Compiling C

Implementing Local Optimizations

Local optimizations are implemented on basic blocks by scanning the basic
block in instruction execution order, looking for optimization opportunities.
1. Determine that the two addi operations return the same result by observing that the operand
x is the same and that the value of its address has not been changed between the two addi
operations.
2. Replace all uses of R106 in the basic block by R101.
3. Observe that i cannot change between the two lw instructions that reference it. So replace
all uses of R107 with R101.
4. Observe that the mul instructions now have the same input operands, so that R108 may be
replaced by R102.
5. Observe that now the two add instructions have identical input operands (R100 and R102),
so replace the R109 with R103.
6. Use dead store code elimination to delete the second set of addi,lw, mul, and add instructions
since their results are unused.
RISC V ARCHITECTURE
Compiling C

Implementing Global Optimizations

To understand the challenge of implementing global optimizations, let’s
consider a few examples:

■ Consider the case of an opportunity for common subexpression

elimination, say, of an IR statement like add Rx, R20, R50.

■ Consider the second lw of i into R107 within the earlier example: how do
we know whether its value is used again?

■ Finally, consider the load of k in our loop, which is a candidate for code
motion. In this simple example, we might argue that it is easy to see that k
is not changed in the loop and is, hence, loop invariant.
RISC V ARCHITECTURE
Compiling C
A control flow graph for the while
loop example.
RISC V ARCHITECTURE
Compiling C
The control flow graph showing the representation of the while
loop example after code motion and induction variable elimination
RISC V ARCHITECTURE
Compiling C
Register Allocation

Register allocation is perhaps the most important optimization for

modern load-store architectures.

Furthermore, register allocation enhances the value of other

optimizations, such as common subexpression elimination.

Modern global register allocation uses a region-based approach, where

a region (sometimes called a live range) represents a section of code
during which a particular variable could be allocated to a particular
register.
RISC V ARCHITECTURE
Compiling C
Region selection- The process is iterative:

The control flow graph showing the

representation of the while loop example after
code motion and induction variable elimination
and register allocation, using the RISC-V register
names.
RISC V ARCHITECTURE
Compiling C
Compiling C:Major types of optimizations and explanation of each class
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
Fallacies

Powerful instruction  higher performance

• Fewer instructions required
• But complex instructions are hard to implement
• May slow down all instructions, including simple ones
• Compilers are good at making fast code from simple instructions

Use assembly code for high performance

• But modern compilers are better at dealing with modern processors
• More lines of code  more errors and less productivity
• writing in assembly language are the protracted time spent coding and
debugging, the loss in portability, and the difficulty of maintaining such
code
 RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
Fallacies
Backward compatibility  instruction set doesn’t change
But they do accrete more instructions

Growth of x86 instruction set over time.

RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set

Pitfalls

Sequential words are not at sequential addresses

Increment by 4, not by 1!

Keeping a pointer to an automatic variable after procedure returns

e.g., passing pointer back via an argument
Pointer becomes invalid when stack popped
RISC V ARCHITECTURE
The Rest of the RISC-V Instruction Set
Concluding Remarks

The two principles of the stored-program computer are the use of instructions
that are indistinguishable from numbers and the use of alterable memory for
programs.

Design principles
1. Simplicity favors regularity
2. Smaller is faster
3.Good design demands good compromises
Make the common case fast
Layers of software/hardware
Compiler, assembler, hardware
RISC-V: typical of RISC ISAs compared
to x86
 THANK YOU

Vanamala H R
Department of Electronics and Communication