Microprocessor and Microcontroller

KEE 602
Unit-1
8085 Interrupts

Neeraj Gupta
Asst. Prof.
EN Department
Contents
1. Introduction
2. Classification
3. Interrupt Architecture
4. Hardware Interrupts
a) Interrupt Execution Sequence
5. Software Interrupt
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6. SIM
8085 Interrupts
7. RIM
Neeraj Gupta
Asst Prof. EN Deptt
1. Introduction
Interrupt is a process where an external device can get the attention of the
microprocessor.

The process starts from the I/O device.

The process is asynchronous.

An interrupt is considered to be an emergency signal that may be serviced.

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The Microprocessor may respond to it as soon as possible.
8085 Interrupts
What happens when MP is interrupted ?
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When the Microprocessor receives an interrupt signal, it suspends the currently Asst Prof. EN Deptt

executing program and jumps to an Interrupt Service Routine (ISR) to respond to

the incoming interrupt.

Each interrupt will most probably have its own ISR.

2. Classification of Interrupts
Hardware and Software Interrupts
• The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, lf a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR).
• The hardware interrupts are initiated by an external device by placing an appropriate signal
at the interrupt pin of the processor. If the interrupt is accepted, then the processor executes
an interrupt service routine (ISR).

Vectored and Non-Vectored Interrupts

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• In vectored interrupts, the processor automatically branches to the specific address in 8085 Interrupts
response to an interrupt.
• In non-vectored interrupts the interrupted device should give the address of the interrupt Neeraj Gupta
service routine (ISR). In vectored interrupts, the manufacturer fixes the address of the ISR Asst Prof. EN Deptt
to which the program control is to be transferred. The vector addresses of hardware
interrupts are given in table.
• The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
• The INTR is a non-vectored interrupt
2. Classification of Interrupts
Maskable and Non-maskable Interrupts
• Masking is preventing the interrupt from disturbing the main program. When an interrupt is
masked the processor will not accept the interrupt signal. The interrupts can be masked by
moving an appropriate data (or code) to accumulator and then executing SIM instruction.
(SIM - Set Interrupt Mask).
• The status of maskable interrupts can be read into accumulator by executing RIM
instruction (RIM - Read Interrupt Mask).
• All the hardware interrupts, except TRAP are disabled, when the processor is resetted.
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• They can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
8085 Interrupts
• To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-
Enable Interrupt).
Neeraj Gupta
Asst Prof. EN Deptt
3. Interrupt Architecture

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
4. Hardware Interrupts
TRAP:
• The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal
has to make a low to high transition and then it has to remain high until the interrupt is
recognized. • It has the highest priority among interrupt signals, it need not to be enabled,
and it can not be disabled. Its vector location is 0024H.

RST 7.5
• The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt
signal has to make a low to high transition an it need not remain high until it is recognized. Unit-I
Vector Location: 003CH 8085 Interrupts
• Since the value has been stored in the flip flop, the line does not have to be high when the
microprocessor checks for the interrupt to be recognized. Neeraj Gupta
Asst Prof. EN Deptt
RST 6.5 and 5.5
• The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts
the interrupting signal should remain high until it is recognized.
• Vector Location: 0034 and 002CH respectively
4.1 Interrupt Execution Sequence

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8085 Interrupts

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Asst Prof. EN Deptt
4.1 Interrupt Execution Sequence

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8085 Interrupts

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Asst Prof. EN Deptt
4.1 Interrupt Execution Sequence

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
5. Software Interrupt: Restart Instruction
• In 8085 Instruction set, RSTn is actually standing for “Restart n”.
• And in this case, n has a value from 0 to 7 only.
• Thus the eight possible RST instructions are there, e.g. RST 0, RST 1, …, RST 7. They are
1-Byte call instructions.
• RST n = CALL n * 8
• For example, let us consider RST 4 is functionally equivalent to CALL 4*8, i.e. CALL 32 =
CALL 0020H. The advantage of RST 2 is that it is only 1 Byte, whereas CALL 0010H is 3-
Byte long. Thus RST instructions are useful for branching to frequently used subroutines.
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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
6. SIM
• In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction. The main uses of SIM instruction are –
• Masking/unmasking of RST7.5, RST6.5, and RST5.5
• Reset to 0 RST7.5 flip-flop
• Perform serial output of data

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8085 Interrupts

•This is the Mask Set Enable (MSE) bit. This bit can have two values: 0 or 1.
If MSE bit = 0, SIM instruction is not being used for masking or unmasking of Neeraj Gupta
interrupts. In such a case, the LS 3 bits of the Accumulator are not having any Asst Prof. EN Deptt
useful information.
•If MSE bit = 1, the SIM instruction is used for masking or unmasking of
interrupts. Then the LS 3 bits provide information about masking or unmasking of
interrupts.
6. SIM
• In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction. The main uses of SIM instruction are –
• Masking/unmasking of RST7.5, RST6.5, and RST5.5
• Reset to 0 RST7.5 flip-flop
• Perform serial output of data

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
This is mask RST7.5 (M7.5) bit. This bit is meaningful only if MSE bit = 1.
If MSE = 1 and M7.5 = 0,RST 7.5 is unmasked.
If MSE = 1 and M7.5 = 1, RST 7.5 is masked.
6. SIM
• In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction. The main uses of SIM instruction are –
• Masking/unmasking of RST7.5, RST6.5, and RST5.5
• Reset to 0 RST7.5 flip-flop
• Perform serial output of data

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
Bit 1: This is M6.5 bit, used for masking/unmasking of RST6.5. It is
similar to M7.5 bit.
Bit 0: This is M5.5 bit, used for masking/unmasking of RST5.5. It is
similar to M7.5 bit.
6. SIM
• In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction. The main uses of SIM instruction are –
• Masking/unmasking of RST7.5, RST6.5, and RST5.5
• Reset to 0 RST7.5 flip-flop
• Perform serial output of data

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8085 Interrupts
Bit D4: Bit 4 (R7.5) of Accumulator is used for
resetting to 0 RST 7.5 flip-flop output when SIM Neeraj Gupta
instruction is executed. Asst Prof. EN Deptt

If R7.5 = 0, SIM instruction is not being used for

resetting of RST7.5 flip-flop. Thus, if R7.5 = 0,
there is no change in the RST7.5 flip-flop output.
If R7.5 = 1, the RST 7.5flip-flop gets cleared.
6. SIM
• In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction. The main uses of SIM instruction are –
• Masking/unmasking of RST7.5, RST6.5, and RST5.5
• Reset to 0 RST7.5 flip-flop
• Perform serial output of data

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
7. RIM
• In 8085 Instruction set, Read Interrupt Mask. It is a 1-Byte multi-purpose instruction. It is
used for the following purposes.
• To check whether RST7.5, RST6.5, and RST5.5 are masked or not;
• To check whether interrupts are enabled or not;
• To check whether RST7.5, RST6.5, or RST5.5 interrupts are pending or not;
• To perform serial input of data.

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
7. RIM

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8085 Interrupts

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Asst Prof. EN Deptt
7. RIM

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8085 Interrupts

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Asst Prof. EN Deptt
7. RIM

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8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt
THANK YOU Unit-I
8085 Interrupts

Neeraj Gupta
Asst Prof. EN Deptt