Vidyalankar Polytechnic

Program: Computer Engineering (NBA Accredited)

Academic Year: 2020-2021

Course: Microprocessor
Course Code: 22415

Presented By: Prof. Sheetal Shelar

Teaching and Examination scheme:
Course Outcomes:
Why Microprocessor?

https://www.youtube.com/watch?v=AkFi90lZmXA
https://www.youtube.com/watch?v=p3q5zWCw8J4
Unit 1- 8086-16 Bit Microprocessor - 14 Marks
 Topics and Subtopics
1) 8086 Pin Function
2) 8086 working
3) Registers of 8086
4) Calculation of Physical address for the given segmentation of 8086
What is a Computer?

A computer is an electronic device that manipulates information, or data. It has the ability
to store, retrieve, and process data. You may already know that you can use a computer
to type documents, send email, play games, and browse the Web. You can also use it to edit
or create spread sheets, presentations, and even videos

A computer is a machine that can be instructed to carry out sequences of arithmetic or logical
operations automatically via computer programming..
Basic Blocks of a computer

All computers consist of :

1. Microprocessor Unit (MPU) MPU is the brain of microcomputer
2. Program Memory (ROM)
3. Data Memory (RAM)
4. Input / Output ports
5. Bus System
8086 microprocessor:
What is a Microprocessor?

Computer's Central Processing Unit (CPU) built on a single Integrated Circuit

(IC) is called a microprocessor

It is a programmable, multipurpose, clock -driven, register-based electronic device that

reads binary instructions from a storage device called memory, accepts binary data as
input and processes data according to those instructions and provides results as output.
Evolution of Microprocessor
Important Features:
Bus:
A Bus is a collection of lines, which perform the same logical task.
*The size of bus indicates the number of lines in it. And hence the number of bits of the bus can
carry – as one line carries one bit of information.
Features of 8086 microprocessor:
1) It has a 16 bit data bus-D0- D15

2) 8086 has a 20 bit address lines can access up to.(220 = 1MB)

Therefore , 20 address lines that is A0 to A19 memory locations.

The address range for this memory is 00000H to FFFFFH.

3) It provides 14 16-bit registers. AX,BX,CX,DX,CS,SS,DS,ES,BP,SP,SI,DI,IP &

FLAG REGISTER.

4) It has multiplexed address and data bus AD0-AD15.

5) Interrupts:-8086 has 256 vectored interrupts.

Architecture or Functional Block Diagram of 8086:
8086 Microprocessor is divided into two functional units, i.e.,
EU (Execution Unit) and BIU (Bus Interface Unit).
FUNCTIONS OF BUS INTERFACE UNIT (BIU):

The Bus Interface Unit (BIU) manages the data, address and control buses.
The BIU functions in such a way that it:
•Fetches the sequenced instruction from the memory,
•Finds the physical address of that location in the memory where the instruction is stored and
•Manages the 6-byte pre-fetch queue where the pipelined instructions are stored.

An 8086 microprocessor exhibits a property of pipelining the instructions in a queue while

performing decoding and execution of the previous instruction.
This saves the processor time of operation by a large amount.
This pipelining is done in a 6-byte queue.
FUNCTIONS OF BUS INTERFACE UNIT (BIU):

Also, the BIU contains 4 segment registers. Each segment register is of 16-bit. The segments are
present in the memory and these registers hold the address of all the segments.
These registers are as follows:

1.Code segment register: It is a 16-bit register and holds the address of the instruction or program
stored in the code segment of the memory.
Also, the IP in the block diagram is the instruction pointer which is a default register that is used by
the processor in order to get the desired instruction. The IP contains the offset address of the next
byte that is to be taken from the code segment.

2. Stack segment register: The stack segment register provides the starting address of stack segment
in the memory. Like in stack pointer, PUSH and POP operations are used in this segment to give and
take the data to/from it.
FUNCTIONS OF BUS INTERFACE UNIT (BIU):

3. Data segment register: It holds the address of the data segment. The data segment stores the data
in the memory whose address is present in this 16-bit register.

4. Extra segment register: Here the starting address of the extra segment is present. This register
basically contains the address of the string data.
It is to be noteworthy that the physical address of the instruction is achieved by combining the
segment address with that of the offset address.

6-byte pre-fetch queue: This queue is used in 8086 in order to perform pipelining. As at the time of
decoding and execution of the instruction in EU, the BIU fetches the sequential upcoming
instructions and stores it in this queue.

The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this
queue. The queue exhibits FIFO behavior., first in first out.
EU (Execution Unit)

The Execution Unit (EU) performs

1.To tell BIU to fetch the instructions or data from memory
2.To decode the instructions.
3.To generate different internal and external controls signal.
4.To execute the instructions.
5.To perform Arithmetic and Logic Operations
Control Unit:
Like the timing and control unit in 8085 microprocessor, the control unit in 8086 microprocessor
produces control signal after decoding the opcode to inform the general purpose register to release the
value stored in it. And it also signals the ALU to perform the desired operation.

ALU:
The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU.
The result of the operation is stored in the desired register.
EU (Execution Unit)

Flag:
Like in 8085, here also the flag register holds the status of the result generated by the ALU. It has
several flags that show the different conditions of the result.

Operand:
It is a temporary register and is used by the processor to hold the temporary values at the time of
operation.
The reason behind two separate sections for BIU and EU in the architecture of 8086 is to perform
fetching and decoding-executing simultaneously.
Concept Of Pipelining:

INSTRUCTION

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Concept Of Pipelining:
Concept Of Pipelining:

1.The process of fetching the next instruction when the present instruction is
being executed is called as pipelining.
2.Pipelining has become possible due to the use of queue.
3.BIU (Bus Interfacing Unit) fills in the queue until the entire queue is full.
4.BIU restarts filling in the queue when at least two locations of queue are
vacant.
5.Advantages of pipelining:
•The execution unit always reads the next instruction byte from the queue in BIU.
This is faster than sending out an address to the memory and waiting for the next
instruction byte to come.
•In short pipelining eliminates the waiting time of EU and speeds up the
processing. -The 8086 BIU will not initiate a fetch unless and until there are two
empty bytes in its queue. 8086 BIU normally obtains two instruction bytes per
fetch.
Register organisation In 8086:
Registers in 8086 are divided into following types:
1. General purpose registers
2. Segment registers
3. Pointers and Index
registers
4. Flag
General purpose registers In 8086:

AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers
AH and AL to also perform 8-bit instructions.
It is generally used for arithmetical and logical instructions but in 8086
microprocessor it is not mandatory to have accumulator as the destination operand.

BX – This is the base register. It is of 16 bits and is divided into two 8-bit registers
BH and BL to also perform 8-bit instructions.
It is used to store the value of the offset.

CX – This is the counter register. It is of 16 bits and is divided into two 8-bit registers
CH and CL to also perform 8-bit instructions.
It is used in looping and rotation.

DX – This is the data register. It is of 16 bits and is divided into two 8-bit registers
DH and DL to also perform 8-bit instructions.
It is used in multiplication an input/output port addressing.
Pointers and Index registers In 8086:
1.SP – This is the stack pointer. It is of 16 bits.
It points to the topmost item of the stack. If the stack is empty the stack pointer will be
(FFFE)H. It’s offset address relative to stack segment.
2.BP – This is the base pointer. It is of 16 bits.
It is primary used in accessing parameters passed by the stack. It’s offset address
relative to stack segment.

3.SI – This is the source index register. It is of 16 bits.

It is used in the pointer addressing of data and as a source in some string related
operations. It’s offset is relative to data segment.

4.DI – This is the destination index register. It is of 16 bits.

It is used in the pointer addressing of data and as a destination in some string related
operations. It's offset is relative to extra segment.
Segment registers In 8086:
Segment registers In 8086:

Code Segment Register (CS)

The code segment of program memory has all the code instructions. The code
segment register stores the base address of the code segment.

Data Segment Register (DS)

The data segment contains the data of the program and this register holds the
base address of the data segment.
Segment registers In 8086:

Stack Segment Register (SS)

The stack segment of program memory contains return addresses, input parameters, return
values of function calls. The stack segment register stores the starting addresses of the stack
segment. The value of the stack segment register is added to an offset value to access any
location within that segment.

Extra Segment Register (ES)

The Extra Segment (ES) register provides additional storage. In 80386 microprocessors, two
additional segment registers were added which are Far Segment Register (FS) and Global
Segment register (GS) which allows the memory access up to 6x64KB= 384K bytes. ES
register holds the base address of the extra segment.
Flag registers In 8086:
 Flag registers In 8086:

The Flag or Status register is a 16-bit register which contains 9 flags, and the remaining 7 bits are
idle in this register. These flags tell about the status of the processor after any arithmetic or logical
operation. IF the flag value is 1, the flag is set, and if it is 0, it is said to be reset.
BB
CF-Carry Flag : It is set when carry/borrow is generated out of MSB of result.
(i.e. D7 bit for 8-bit operation, D15 bit for a 16 bit operation).

PF-ParityFlag : It is set if the result has even Parity.

AF-Auxiliary Carry Flag :This is set if a carry is generated out of the lower nibble,
(i.e. From D3 to D4 bit)to the higher nibble.

ZF-Zero Flag : This flag is set if the result is zero after performing ALU operations.
Otherwise it is reset
 SF-Sign Flag : This flag is set if the MSB of the result is equal to 1 after performing ALU
operation , otherwise it is reset.

OF-Overflow Flag : This flag is set if an overflow occurs, i.e. if the result of a
signed operation is large enough to be accommodated in destination register

Control Flags:

TF-Trap Flag : If this flag is set ,the processor enters the single step execution
mode.
IF-Interrupt Flag : It is used to mask(disable) or unmask(enable)the INTR interrupt.

DF-Direction flag : It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower memory
address and vice-a-versa.
Segmentation:

Memory is one of the most important resources on a computing system, In order to use memory
efficiently and effectively a number of techniques have been developed to properly manage it.
One of these memory management techniques is known as Memory Segmentation (MS)

Segmentation is the process in which the main memory of the computer is logically divided
into different segments and each segment has its own base address. It is basically used to
enhance the speed of execution of the computer system, so that the processor is able to fetch
and execute the data from the memory easily and fast.
Segmentation:
 The number of address lines in 8086 is 20, 8086 BIU will send
20bit address, so as to access one of the 1MB memory locations.

 The four segment registers actually contain the upper 16 bits of

the starting addresses of the four memory segments of 64 KB
each with which the 8086 is working at that instant of time

 A segment is a logical unit of memory that may be up to 64

kilobytes. Starting address will always be changing. It will not be
fixed.

 Note that the 8086 does not work the whole 1MB memory at
any given time. However, it works only with four 64KB
segments within the whole 1MB memory.
Segment Registers:
Segment Registers:

Segment Registers of 8086 Microprocessor are located in the Bus Interface Unit of the microprocessor.
A segment register (e.g., cs) points at the beginning of a segment in memory.

Segment Registers are divided in to:

Data Segment, Code Segment, Extra Segment and Stack Segment.
CS register:
The CS register points at the segment containing the currently executing machine instructions.

Note that, despite the 64K segment limitation, 8086 programs can be longer than 64K.

You simply need multiple code segments in memory. Since you can change the value of the cs
register, you can switch to a new code segment when you want to execute the code located there.
Segment Registers:
DS register :

Points to the data segment of the memory where the data is stored.

Again, you’re limited to 65,536 bytes of data in the data segment;

but you can always change the value of the ds register to access additional data in other segments.

ES register:
Points to a segment in the memory which is another data segment in the memory.
SS register:

Is used for addressing stack segment of the memory. The stack segment is that segment of memory
which is used to store stack data.
Register organisation In 8086:
Physical address generation:

Each Segment has a corresponding 16-bit Segment Register which holds the Base Address (starting Address)
of the Segment.
At any given time, 8086 can address 16-bit x 64KB = 256 KB of memory chunk out of 1MB.

To locate any address in the memory bank, it needs the Physical address of that memory location. It cannot
get the 20-bit Physical address using the 8086 Address Line or 16-bit Segment Registers alone.

In order to access memory location, you cannot pass 20-bit address directly to the processor. You need to
tell the 16-bit address with respect to the segment.
This 16-bit address with respect to the part (segment of 64KB) of the memory bank is called the offset.

Physical address=Segment base address*10+Offset (Effective) address

=1000H*10+1100H
=11100H.
Physical address generation:
Physical address generation:

If DS=345AH and SI=13DCH.

Calculate physical address

DS=345AH and SI=13DCH

Physical address = DS*10H + SI

= 345AH * 10H + 13DCH
= 345A0+13DC
=3597CH
PIN Configuration of 8086:
 PIN Configuration of 8086:

8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip.
Let us now discuss in detail the pin configuration of a 8086 Microprocessor.

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

AD0-AD15 : Address/Data bus. These are low order address bus. They are multiplexed with
data. When AD lines are used to transmit memory address the symbol A is used instead of AD,
for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of
AD, for example D0-D7, D8-D15 or D0-D15.
 PIN Configuration of 8086:
A16-A19 : High order address bus. These are multiplexed with status signals.
S2, S1, S0 : Status pins. These pins are active during T4, T1 and T2 states and is returned to passive
state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for
generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during
T4 indicates the beginning of a bus cycle.
PIN Configuration of 8086:
A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
PIN Configuration of 8086:
BHE’/S7 : Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE
(Active Low) signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.

RD’: This is used for read operation. It is an output signal. It is active when low.

READY : This is the acknowledgement from the memory or slow device that they have completed
the data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the microprocessor. The signal is active high(1).

INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request is found pending,
the processor enters the interrupt acknowledge cycle. This can be internally masked after resulting the
interrupt enable flag. This signal is active high(1) and has been synchronized internally.
PIN Configuration of 8086:

NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system
memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1) initiates
the interrupt at the end of the current instruction. This input has been synchronized internally.

INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge cycle.

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to forc the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of
the pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
 PIN Configuration of 8086:

LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain
control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else
the processor remains in an idle state. The input is internally synchronized during each of the clock cycle on
leading edge of the clock.

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus
control activity. Its an asymmetric square wave with a 33% duty cycle.
PIN Configuration of 8086:

RESET : This pin requires the microprocessor to terminate its present activity immediately.
The signal must be active high(1) for at least four clock cycles.

Vcc : Power Supply( +5V D.C.)

GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according
to the table shown below
PIN Configuration of 8086:

DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or
8287 data bus transceiver. The direction of data flow is controlled through the transceiver.

DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum
system which uses transceiver. DEN is active low(0) during each memory and input-output access
and for INTA cycles.

HOLD/HLDA : HOLD indicates that another master has been requesting a local bus .This is
an active high(1). The microprocessor receiving the HOLD request will issue HLDA (high)
as an acknowledgement in the middle of a T4 or T1 clock cycle.

ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the
8282 or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is
never floated, is always integer.
Thank You!!!