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Central Processing Unit 2 Lecture 22

Overview
 Peripheral Devices

 Input-Output Interface

 Asynchronous Data
Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor

 Serial Communication

CSE 211, Computer Organization and Architecture

Input/Output Organization 4

Input Output Organization

I/O Subsystem
 Efficient Mode Of Communication
 between central system and outside environment
 Programmed, Input Data, Process, Record, Display Results.
 Slow Keyboard Processor Idles Waiting For Slow Input.
 time of waiting is more for information to arrive
 E.G. Magnetic Tapes, Disks
Input/Output Organization 5

Peripheral Devices

• Devices under direct control of computer are

connected on-line.

• Peripherals I/O devices attached to the computer

• There are three types of peripherals :

• Input peripherals
• Output peripherals
• Input-output peripherals
Input/Output Organization 6

Peripheral Devices

Peripheral (or I/O Device)

Monitor (Visual Output Device) : CRT, LCD

KeyBoard (Input Device) : light pen, mouse, touch screen, joy stick, digitizer

Printer (Hard Copy Device) : Daisy wheel, dot matrix and laser printer

Storage Device  Magnetic tape, magnetic disk, optical disk

Input/Output Organization 7

Peripheral Devices
Input Devices Output Devices
• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Daisy Wheel, Dot Matrix, Laser)
- Paper Tape Reader • Plotter
- Bar code reader
- Optical Mark Reader
• Magnetic Input Devices
- Magnetic Stripe Reader
(ATM)
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
•
Input/Output Organization 9

Input Output Organization

 ASCII (American Standard Code for Information Interchange)

• I/O communications usually involves data transfer

• Alphanumeric information from device and the computer.

• Standard binary code for alphanumeric character is ASCII

• ASCII Code :
• It uses 7 bits to code 128 characters
• 7 bit - 00 - 7F ( 0 - 127 )
Input/Output Organization 10

Input Output Organization

 ASCII (American Standard Code for Information Interchange)

• ASCII is 7 bits but,

most computers manipulate 8 bit quantity as a
single unit called byte.

80 - FF ( 128 - 255 ) : Greek, Italic type font

• Three types of control characters: Format effectors, Information

separators and communication control
Input/Output Organization 11

Input Output Organization

 Format effectors control printing layout.

Examples: backspace (BS), horizontal tab (HT),

Carriage return (CR) is also included.

 Information separators divide data sections, divisions like paragraphs

and pages.

Examples: record (RS), file separator (FS).

 Communication control: transmission of text between remote terminals

STX(Start of text) and ETX(end of text).

Input/Output Organization 13

I/O Interface
• Provides a method for transferring information

• Transfer between internal storage and external I/O devices

• (such as memory and CPU registers)

• Resolves the differences between the computer and peripheral

devices

(1). Peripherals – Electromechanical or Electromagnetic Devices

CPU or Memory - Electronic Device
– Conversion of signal values required
Input/Output Organization 14

I/O Interface

(2). Data Transfer Rate

• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
– Some kinds of Synchronization mechanism may be needed

(3). Data formats or Unit of Information

• Peripherals – Byte, Block, …
• CPU or Memory – Word

(4). Operating modes of peripherals may differ

• must be controlled so that not to disturbed other peripherals connected to CPU
Input/Output Organization 15

I/O Bus and Interface

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal
Input/Output Organization 16

I/O Bus and Interface

Interface :
- Decodes the device address (device code)

- Decodes the commands (operation)

- Provides signals for the peripheral controller

- Synchronizes the data flow and supervises

the transfer rate between peripheral and CPU or Memory

4 types of command interface can receive : control, status, data o/p and data i/p
Input/Output Organization 17

I/O Bus and Interface

• Control command :
• issued to activate peripheral and to inform what to do

• Status command :
• used to test various status condition in interface and peripherals

• data o/p command :

• causes the interface to respond by transferring data
• From the bus into one of its registers

• data i/p command :

• interface receives an item of data from the peripheral
• Then, places it in its buffer register.
Input/Output Organization 18

I/O Bus and Memory Bus

Functions of Buses

• MEMORY BUS is for information transfers between CPU and the MM

• I/O BUS is for information transfers.

• Transfer between CPU and I/O devices through their I/O interface
Input/Output Organization 19

I/O Bus and Memory Bus

• 3 ways to bus can communicate with memory and I/O :

(1). use two separate buses,

• one to communicate with memory , the other with I/O interfaces
- Computer has independent set of data, address and control bus
- one for accessing memory and another I/O.
- done in computers that have separate IOP other than CPU.

(2). Use one common bus for memory and I/O but separate control lines
for each

(3). Use one common bus for memory and I/O with common control
lines for both
 Asynchronous Data Transfer

Synchronous Data Transfer:

• Uses a common clock for all registers.

• Data transfer occurs simultaneously with clock pulses.
• CPU and I/O Interface operate independently but share a clock for transfer.

Asynchronous Data Transfer:

• Each unit (CPU & Interface) has its own independent clock.
• Control signals are required to synchronize data transfer
• Each unit uses its own private clock for internal registers.
• Asynchronous data transfer between two independent units requires that
control signals
 Asynchronous Data Transfer

Two methods:

• STROBE: A control signal indicates when data is transmitted.

• HANDSHAKING: A mutual agreement between units for data transfer

Source initiated strobe:

1 1

2
2
Destination initiated strobe:

1 1
Source initiated handshaking:
Timeout : If the return handshake signal does not respond within a given time period,
the unit assumes that an error has occurred.
• Asynchronous Serial Transfer
• Synchronous transmission :
• The two unit share a common clock frequency
• Bits are transmitted continuously at the rate dictated by the clock pulses
• Asynchronous transmission :
• Binary information sent only when it is available and line remain idle
otherwise
• Special bits are inserted at both ends of the character code
• Each character consists of three parts :
• 1) start bit : always “0”, indicate the beginning of a character
• 2) character bits : data
• 3) stop bit : always “1”

1 1 0 0 0 1 0 1

S ta rt S to p
C ha ra c ter b its
b it b it
• Asynchronous transmission rules :
•  When a character is not being sent, the line is kept in the 1-state
•  The initiation of a character transmission is detected from the start bit,
which is always “0”
•  The character bits always follow the start bit
•  After the last bit of the character is transmitted, a stop bit is detected
when the line returns to the 1-state for at least one bit time

• Baud Rate : Data transfer rate in bits per second

• 10 character per second with 11 bit format = 110 bit per second
Input/Output Organization 29

Universal Asynchronous Receiver Transmitter

A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control

Internal Bus
and clock
Chip select CS
Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of
stop bits
•UART stands for?

a. Universal Asynchronous Sender Receiver

b. Universal Asynchronous Receiver Transmitter
c. Universal Synchronous Receiver Transmitter
d. None Of These.
 Overview

 Peripheral Devices

 Input-Output Interface

 Asynchronous Data Transfer

 Modes of Transfer

 Priority Interrupt

 Direct Memory Access

 Input-Output Processor
 Modes of Transfer

Binary information received from external device is usually stored

in memory.

Information transferred from central computer into an external

device originates in the memory unit.

The CPU merely execute I/O instructions and may accept data
temporarily but ultimate source or destination is the Memory Unit.
 Modes of Transfer

Data transfer between central computer and I/O devices may be

handled in a variety of modes.
Some modes use CPU as intermediate path,

• others transfer data directly to and from memory unit.

Data Transfer to or from peripheral can be handled in one of
three possible modes :

 Programmed I/O
 Interrupt-Initiated I/O
 Direct Memory Access (DMA)
Input/output Organization 34

Modes of Transfer – Programmed I/O

 Programmed I/O
- Programmed I/O operations are the result of I/O Instructions written in computer
program.

- Each data item transfer is initiated by an instruction in the program.

- Usually, transfer is to and from a CPU register to peripheral.

- Other instructions are needed to transfer data to and from CPU and Memory

- Transferring data under program control requires constant monitoring of the

peripheral by CPU.
• In programmed I/O method,

• CPU stays in a program loop until the I/O unit indicated that it is
ready for data transfer.
• This is a time consuming process since it keeps the processor
busy needlessly.
• It can be avoided by using Interrupt facility and special
commands
• Interrupt to inform the interface to issue an interrupt request
signal when data are available for the device.
 Interrupted I/O

• In the programmed I/O method, the CPU stays in a program loop until the I/O unit
indicates that it is ready for data transfer.

• This is a time-consuming process since it keeps the processor busy needlessly.

• It can be avoided by using an interrupt facility and special commands to inform the
interface to issue an interrupt request signal when the data are available from the device.

• In the meantime the CPU can proceed to execute another program. The interface
meanwhile keeps monitoring the device.
 Interrupted I/O

• When the interface determines that the device is ready for data transfer, it generates an
interrupt request to the computer.

• Upon detecting the external interrupt signal, the CPU momentarily stops the task it is
processing,

• Then, Branches to a service program to process the I/O transfer, and then returns to the
task it was originally performing.
 DMA
1. Transfer of data under programmed I/O is between CPU and peripheral.

2. In direct memory access (DMA), the interface transfers data into and out of the memory unit through the
memory bus.

3. The CPU initiates the transfer by supplying the interface with the starting address and the number of words
needed to be transferred and then proceeds to execute other tasks.

4. When the transfer is made, the DMA requests memory cycles through the memory bus.

5. When the request is granted by the memory controller, the DMA transfers the data directly into memory.

6. The CPU merely delays its memory access operation to allow the direct memory I/O transfer.

7. Since peripheral speed is usually slower than processor speed, I/O-memory transfers are infrequent
compared to processor access to memory.
 Priority Interrupts

Priority

- Determines which interrupt is to be served first,

• when two or more requests are made simultaneously

- Also determines which interrupts are permitted to interrupt the computer,

• while another is being serviced

- Higher priority interrupts can make requests while servicing a lower priority
interrupt
 Priority Interrupts

A priority interrupt is a system that establishes priority over the

various sources to determine

- which condition is to serviced first when two or more requests

arrive simultaneously

-which conditions are permitted to interrupt the computer while

another request is being serviced
 Priority Interrupts

Priority Interrupt by Software (Polling)

Polling procedure is used to identify highest priority source by software

means

- common branch address for all the interrupts

- Priority is established by the order of polling the devices(interrupt sources)

- highest priority device is tested first and if interrupt is on ,

- control branches to service routine for this source otherwise next lower priority source is tested
 Priority Interrupts

- Flexible since it is established by software

- Low cost since it needs a very little hardware

- Very slow

- if there are many interrupt time required to poll may exceed time available to
service IO device
 Priority Interrupts

Priority Interrupt by Hardware

- Require a priority interrupt manager which accepts all the interrupt requests
to determine the highest priority request

- Fast since identification of the highest priority interrupt request is identified by

the hardware

- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine

- Can be addressed using serial or parallel connection of interrupt lines.

Example of serial is Daisy chaining Priority
 Hardware Priority Interrupts – Daisy Chain
VAD 1 VAD 2 VAD 3
* Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
To next - Single common line
PI PO PI PO PI PO
device * Interrupt Acknowledge Line
- Daisy-Chain

Interrupt request
INT
CPU
Interrupt acknowledge
INTACK

-Serial connection of all device that request an interrupt

-Device with highest priority placed in first position followed by devices with lower priority and so
on.

-Interrupt generated by any device  signals low state interrupt line

-CPU responds by enabling interrupt acknowledgement (INTACK) line.

- device receives PI=1 and passes to next only when not requesting else PI=0

-Thus device with PI=1 and PO=0 is one with highest priority requesting interrupt
 Hardware Priority Interrupts – Daisy Chain

Example: Daisy chain working

Hardware Priority Interrupts – Daisy Chain
 Parallel Priority Interrupts
Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated
by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
 Interrupt Cycle

At the end of each Instruction cycle

- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle

SP SP - 1 Decrement stack pointer

M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine
Input/Output Organization 51

Direct Memory Access

• Block of data transfer between high speed devices like Disk and Memory

* DMA controller - Interface which takes over the buses to manage the
transfer directly between
• Memory and I/O Device, freeing CPU for other tasks

* CPU initializes DMA Controller by sending memory address and the block
size (number of words)
Input/Output Organization 52

Direct Memory Access

Fig 1: CPU bus signals for DMA transfer (Bus control by DMA)

ABUS Address bus

Bus request BR DBUS Data bus
CPU
Bus granted BG RD Read
WR Write Fig 2: Block diagram of DMA controller

Data bus Data bus Address bus

buffers buffers
Address register:
Contains an address to specify

Internal Bus
DMA select DS
Desired location in memory Address register
RS
Word count register
Read RD Word count register
Holds no. of words to be transferred Write WR Control
logic
Control register Bus request BR Control register
Specifies the mode of transfer
Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device
 Input/Output Organization 53

Direct Memory Access

DMA Transfer can be made in several ways

(1) Burst Transfer :

• a block sequence consisting of memory words is transferred in continuous burst while the DMA
controller is master of memory bus
• This mode of transfer is needed for fast devices such as magnetic disk where data transmission
cannot be stopped or slowed down until an entire block is transferred
 Input/Output Organization 54

Direct Memory Access

(2) Cycle stealing :

• Alternative technique called cycle stealing allows DMA controller to transfer one data
word at time after which it must return control of the buses to the CPU.
• CPU merely delays its operation for one memory cycle to allow the direct memory I/O
transfer to “steal” one memory cycle
Input/Output Organization 55

DMA I/O Operation

DMA is first initialized by CPU. After that DMA starts and continues to transfer data
between memory and peripheral unit until an entire block is transferred.

CPU initializes the DMA by sending following information through data bus:

(1) Starting address of the memory block (for read/write)

(2) Word Count (no. of words in memory block)

(3) Control to specify mode of transfer (E.g. read/write)

(4) A control to start DMA Transfer

Input/Output Organization 57

DMA Transfer

Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data

Read control

Write control

Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS DMA I/O
Controller Peripheral
BR device
BG DMA request

Interrupt
Input/Output Organization 58

I/O Processor - Channel

Channel
- Processor with direct memory access capability that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Unlike DMA Controller, IOP can fetch and execute its own instruction
- IOP Instructions (Commands) specially designed to facilitate I/O transfer.

Central
processing
unit (CPU)

Memory Bus
Peripheral devices
Memory
unit PD PD PD PD
Input-output
processor
(IOP) I/O bus
Input/Output Organization 59

Channel CPU Communication

CPU operations IOP operations

Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word

Check status word to memory location
for correct transfer.

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