ARM MICROCONTROLLER & EMBEDDED

SYSTEMS (17EC62)

ARM Cortex M3 Instruction Sets and Programming

(Lecture-4)
(Lecture-2)
ARM Instruction Sets

1
The Cortex-M3 provides Rotate and Shift Instructions.
 In some cases, the rotate operation can be combined with other operations (for
example, in memory address offset calculation for load/store instructions).
 Again, a 32-bit version of the instruction is used if "S" suffix is not used and if
UAL syntax is used.

Shift and Rotate Instructions

Instruction Operation
ASR Rd, Rn,#immed ; Rd = Rn » immed
ASRRd, Rn ; Rd = Rd » Rn Arithmetic shift right
ASR.W Rd, Rn, Rm ; Rd = Rn » Rm
LSLRd, Rn,#immed ; Rd = Rn « immed Logical shift left
LSLRd, Rn ; Rd = Rd « Rn
LSL.W Rd, Rn, Rm ; Rd = Rn « Rm
LSRRd, Rn,#immed ; Rd = Rn » immed
LSRRd, Rn ; Rd = Rd » Rn Logical shift right
LSR.W Rd, Rn, Rm ; Rd = Rn » Rm
ROR Rd, Rn ; Rd rot by Rn
ROR.W Rd, Rn,#immed ; Rd = Rn rot by immed Rotate right
ROR.W Rd, Rn, Rm ; Rd = Rn rot by Rm
RRX.W Rd, Rn ; {C, Rd} = {Rn, C} Rotate right extended
 Shift and Rotate Instructions
 In UAL syntax, the rotate and shift operations can also update the carry flag if the S
suffix is used (and always update the carry flag if the 16-bit Thumb code is used).
 If the shift or rotate operation shifts the register position by multiple bits, the value of
the carry flag C will be the last bit that shifts out of the register.
 The rotate left operation can be replaced by a rotate right operation with a
different rotate offset.
 For example, a rotate left by 4-bit operation can be written as a rotate right by 28-
bit instruction, which gives the same result and takes the same amount of time to
execute
 For conversion of signed data from byte or half word to word, the Cortex-M3

provides the two instructions. Both 16-bit and 32-bit versions are available. The
16-bit version can only access low registers.
Sign Extend Instructions
Instruction Operation
SXTB Rd, Rm ; Rd = signext(Rm[7:0]) Sign extend byte data into word
SXTH Rd, Rm ; Rd = signext(Rm[15:0]) Sign extend half word data into word

 Another group of data processing instructions is used for reversing data

bytes
in a register. These instructions are usually used for conversion between little

endian and big endian data.

 Both 16-bit and 32-bit versions are available. The 16-bit version can only
access low registers.
Instruction Operation
Data Reverse Ordering Instructions
REV Rd, Rn ; Rd = rev(Rn) Reverse bytes in word

REV16 Rd, Rn ; Rd = rev16(Rn) Reverse bytes in each half word

REVSH Rd, Rn ; Rd = revsh(Rn Reverse bytes in bottom half word and

sign extend the result
The last group of data processing instructions is for Bit field processing.

Bit Field Processing and Manipulation Instructions

Instruction Operation

BFC.W Rd, Rn, #<width> Clear bit field within a register

BFI.W Rd, Rn, #<lsb>, #<width> Insert bit field to a register

CLZ.W Rd, Rn Count leading zero

RBIT.W Rd, Rn Reverse bit order in register

SBFX.W Rd, Rn, #<lsb>, #<width> Copy bit field from source and sign extend it

UBFX.W Rd, Rn, #<lsb>, #<width> Copy bit field from source register
 3. Execution Flow control instructions
Assembler Language: Call and Unconditional Branch:
 The most basic branch instructions are as follows:
B label ; Branch to a labeled address
BX reg ; Branch to an address specified by a register

 In BX instructions, the LSB of the value contained in the register determines the next
state (Thumb/ARM) of the processor.

 In the Cortex-M3, because it is always in Thumb state, this bit should be set to 1. If it is
zero, the program will cause a usage fault exception because it is trying to switch the
processor into ARM state.

 To call a function, the branch and link instructions should be used.

BL label ; Branch to a labeled address and save return address in LR
BLX reg ; Branch to an address specified by a register and save return address in
LR.
 3. Execution Flow control instructions
 With these instructions, the return address will be stored in the link register (LR) and
the function can be terminated using BX LR, which causes program control to return to

the calling process.

 However, when using BLX, make sure that the LSB of the register is 1. Otherwise the
processor will produce a fault exception because it is an attempt to switch to the ARM
state.

 You can also carry out a branch operation using MOV instructions and LDR
instructions. For example,
MOV R15, R0 ; Branch to an address inside R0
LDR R15, [R0] ; Branch to an address in memory location ;
; specified by R0
POP {R15} ; Do a stack pop operation, and change the program counter
 Instruction List
16-Bit Branch Instructions

Instruction Function

B Branch

B<cond> Conditional branch

Branch with link; call a subroutine and store the return address in LR (this
BL is actually a 32-bit instruction, but it is also available in Thumb in
traditional ARM processors)

BLX Branch with link and change state (BLX <reg> only)

BX <reg> Branch with exchange state

CBZ Compare and branch if zero (architecture v7)

CBNZ Compare and branch if nonzero (architecture v7)

IT IF-THEN (architecture v7)

 Instruction List

32-Bit Branch Instructions

Instruction Function

B Branch

B<cond> Conditional branch

BL Branch and link

TBB Table branch byte; forward branch using a table of single byte offset

TBH Table branch half word; forward branch using a table of half word offset
Assembler Language: Decisions and Conditional Branches

 Most conditional branches in ARM processors use flags in the APSR to

determine whether a branch should be carried out. In the APSR, there are five
flag bits; four of them are used for branch decisions.
 There is another flag bit at bit[27], called the Q flag. It is for saturation math
operations and is not used for conditional branches.

Fkg PSR Bit Description

N 31 Negative flag (last operation result is a negative value)

Z 30 Zero (last operation result returns a zero value)

C 29 Carry (last operation returns a carry out or borrow)

V 28 Overflow (last operation results in an overflow)
 Assembler Language: Decisions and Conditional Branches
 The flags might be used for branch decisions, or they can be used as part of the input
for the next instruction. The ARM processor normally contains at least the Z, N, C, and
V flags, which are updated by execution of data processing instructions.

Z (Zero) flag: This flag is set when the result of an instruction has a zero value
or when a comparison of two data returns an equal result.

N (Negative) flag: This flag is set when the result of an instruction has a
negative value (bit 31 is 1).

C (Carry) flag: This flag is for unsigned data processing—for example, in add
(ADD) it is set when an overflow occurs; in subtract (SUB) it
is set when a borrow did not occur (borrow is the invert of carry).

V (Overflow) flag: This flag is for signed data processing; for example, in an
add (ADD), when two positive values added together produce a
negative value, or when two negative values added together produce a
positive value
 With combinations of the four flags (N, Z, C, and V), 15 branch conditions are defined.
Using these conditions, branch instructions can be written as, for example,
BEQ label ; Branch to address 'label' if Z flag is set.
 You can also use the Thumb-2 version if your branch target is further away. For example,
BEQ.W label ; Branch to address 'label' if Z flag is set
Conditions for Branches or Other Conditional Operations
Symbol Condition Flag
EQ Equal Z set
NE Not equal Z clear
CS/HS Carry set/unsigned higher or same C set
CC/LO Carry clear/unsigned lower C clear
MI Minus/negative N set
PL Plus/positive or zero N clear
VS Overflow V set
VC No overflow V clear
HI Unsigned higher C set and Z clear
LS Unsigned lower or same C clear or Z set
GE Signed greater than or equal N set and V set, or N clear and V clear (N == V)
LT Signed less than N set and V clear, or N clear and V set (N != V)
GT Signed greater than Z clear, and either N set and V set, or N clear and V clear (Z == 0, N == V)
LE Signed less than or equal Z set, or N set and V clear, or N clear and V set (Z == 1 or N != V)
AL Always (unconditional) —
The defined branch conditions can also be used in IF-THEN-ELSE structures.
For example,
CMP R0, R1 ; Compare R0 and R1
ITTEE GT ; If R0 > R1 Then if true, first 2 statements execute, if false, other 2
statements execute
MOVGT R2, R0 ; R2 = R0
MOVGT R3, R1 ; R3 = R1
MOVLE R2, R0 ; Else R2 = R1
MOVLE R3, R1 ; R3 = R

Assembler Language: Combined Compare and Conditional Branch

With ARM architecture v7-M, two new instructions are provided on the Cortex-M3 to supply a simple compare
with zero and conditional branch operations. These are CBZ (compare and branch if zero) and
CBNZ (compare and branch if nonzero).
 Assembler Language: Combined Compare and Conditional Branch
 With ARM architecture v7-M, two new instructions are provided on the Cortex-M3 to
supply a simple compare with zero and conditional branch operations. These are CBZ
(compare and branch if zero) and CBNZ (compare and branch if nonzero).

The compare and branch instructions only support forward branches.

For example, i = 5;
while (i != 0 ){ func1(); ; call a function
i--;
}
This can be compiled into the following:
MOV R0, #5 loop1 ; Set loop counter
CBZ R0,loop1exit ; if loop counter = 0 then exit the loop
BL func1 ; call a function
SUB R0, #1 B loop1 ; loop counter decrement
loop1 exit ; next loop
 The usage of CBNZ is similar to CBZ, apart from the fact that the branch is
taken if the Z flag is not set (result is not zero). For example,
status = strchr(email_address, '@');
if (status == 0)
{ //status is 0 if @ is not in email_address
show_error_message();
exit(1);
}

 This can be compiled into the following:...

BL strchr
CBNZ R0, email_looks_okay ; Branch if result is not zero BL
show_error_message BL exit
email_looks_okay
 The APSR value is not affected by the CBZ and CBNZ instructions .
 Conditional Execution Using IT Instructions
 The IT (IF-THEN) block is very useful for handling small conditional code. It
avoids branch penalties because there is no change to program flow. It can provide
a maximum of four conditionally executed instructions. In IT instruction blocks,
the first line must be the IT instruction, detailing the choice of execution, followed
by the condition it checks.

 The first statement after the IT command must be TRUE-THEN-EXECUTE,

which is always written as ITxyz, where T means THEN and E means ELSE.
The second through fourth statements can be either THEN (true) or ELSE (false):

IT<x><y><z> <cond> ;

IT instruction (<x>, <y>, ; <z> can be T or E)

instr1<cond> <operands> ; 1st instruction (<cond> ; must be same as IT)

instr2<cond or not cond> <operands> ; 2nd instruction (can be ; <cond> or <!cond>)

instr3<cond or not cond> <operands> ; 3rd instruction (can be; <cond> or <!cond>)
instr4<cond or not cond> <operands> ; 4th instruction (can be; <cond> or <!cond>)
 Conditional Execution Using IT Instructions
 If a statement is to be executed when <cond> is false, the suffix for the instruction must
be the opposite of the condition.
 For example, the opposite of EQ is NE, the opposite of
GT is LE, and so on. The following code shows an example of a simple conditional
execution:
You can have fewer than four conditionally executed
instructions. The minimum is 1. You need to make sure
the number of T and E occurrences in the IT instruction
If (R1<R2) matches the number of conditionally executed
then instructions after the IT.
R2=R2-R1
R2=R2/2
else R1=R1- If an exception occurs during the IT instruction block,
R2 the execution status of the block will be stored in the
R1=R1/2 stacked PSR (in the IT/Interrupt-Continuable
In Instruction [ICI] bit field). So, when the exception
assembly, handler completes and the IT block resumes, the rest of
CMP R1,
R2 ITTEE If R1 < R2 (less then) the instructions in the block can continue the execution
LT correctly.
SUBLT.W ; then execute instruction 1 and
R2,R1 2(indicated by T) else execute
LSRLT.W instruction 3 and 4 (indicated by E) In the case of using multicycle instructions (for
R2,#1
SUBGE.W 1st instruction 2nd instruction example, multiple load and store) inside an IT block, if
R1,R2 3rd instruction (notice the GE is an exception takes place during the execution, the
LSRGE.W whole instruction is abandoned and restarted after the
R1,#1 opposite of LT) 4th instruction 37
interrupt process is completed.
 Conditional Execution Using IT Instructions
 If a statement is to be executed when <cond> is false, the suffix for the instruction

must be the opposite of the condition.

 For example, the opposite of EQ is NE, the opposite of
GT is LE, and so on. The following code shows an example of a simple conditional
execution:
In
If (R1<R2)
assembly,
then
CMP R1,
R2=R2-R1
R2 ITTEE If R1 < R2 (less then)
R2=R2/2 LT ; then execute instruction 1 and
else R1=R1- 2(indicated by T) else execute
SUBLT.W
instruction 3 and 4 (indicated by E)
R2 R2,R1
1st instruction 2nd instruction
LSRLT.W
R1=R1/2 R2,#1
SUBGE.W
R1,R2 3rd instruction (notice the GE is
LSRGE.W opposite of LT) 4th instruction
R1,#1 37
 Conditional Execution Using IT Instructions
 You can have fewer than four conditionally executed instructions. The minimum
is 1. You need to make sure the number of T and E occurrences in the IT
instruction matches the number of conditionally executed instructions after the
IT.

 If an exception occurs during the IT instruction block, the execution status of the
block will be stored in the stacked PSR (in the IT/Interrupt-Continuable
Instruction [ICI] bit field). So, when the exception handler completes and the IT
block resumes, the rest of the instructions in the block can continue the execution

correctly.

 In the case of using multicycle instructions (for example, multiple load and store)

inside an IT block, if an exception takes place during the execution, the whole
instruction is abandoned and restarted after the interrupt process is completed.
Thank You