ARM MICROCONTROLLER & EMBEDDED

SYSTEMS (17EC62)

ARM Cortex M3 Instruction Sets and Programming

(Lecture-4)
(Lecture-3)
ARM Instruction Sets

1
 4. Special instructions
Assembler Language: Instruction Barrier and Memory Barrier Instructions

 The Cortex-M3 supports a number of barrier instructions. These instructions are

needed as memory systems get more and more complex. In some cases, if
memory
barrier instructions are not used, race conditions could occur.
 The following are the three barrier instructions in the Cortex-M3:
• DMB • DSB • ISB

 The memory barrier instructions can be accessed in C using Cortex

Microcontroller Software Interface Standard (CMSIS) compliant device
driver
library as follows:
void_DMB(void); // Data Memory Barrier
 4. Special instructions
 For example, if the memory map can be switched by a hardware register, after
writing to the memory switching register you should use the DSB instruction.
 Using DSB in this case will make sure that the write to the memory map
switching register is completed before a new instruction is executed.
 The DSB and ISB instructions can be important for self-modifying code.Using
DSB and then ISB can ensure that the modified program code is fetched again.

ISB instruction should be used after updating the value of the CONTROL register.
 DMB is very useful for multi-processor systems.
Barrier Instructions
Instruction Description
DMB Data memory barrier; ensures that all memory accesses are completed before new
memory access is committed\
Data synchronization barrier; ensures that all memory accesses are completed before
DSB
next instruction is executed

ISB Instruction synchronization barrier; flushes the pipeline and ensures that all previous
instructions are completed before executing new instructions
 Assembly Language: Saturation Operations
 The Cortex-M3 supports two instructions that provide signed and unsigned
saturation operations: SSAT and USAT (for signed data type and unsigned data
type, respectively).
 Saturation is commonly used in signal processing—for example, in signal
amplification.
When an input signal is amplified, there is a chance that the output will be larger than
 If the value is adjusted simply by removing the unused MSB, an overflowed result will
the allowed
cause output
the signal range. to be completely deformed.
waveform
 The saturation operation does not prevent the distortion of the signal, but at least the
amount of distortion is greatly reduced in the signal waveform.
 Assembly Language: Saturation Operations

Saturation Instructions

Instruction Description
SSAT.W <Rd>, #<immed>, <Rn>,
{,<shift>} Saturation for signed value
USAT.W <Rd>, #<immed>, <Rn>, Saturation for a signed value into an
{,<shift>} unsigned value

Rn: Input value

Shift: Shift operation for input value before saturation; optional, can be #LSL N or
#ASR N Immed: Bit position where the saturation is carried out Rd: Destination
register
 Besides the destination register, the Q-bit in the APSR can also be affected by
the result. The Q flag is set if saturation takes place in the operation, and it can
be cleared by writing to the APSR
 For example, if a 32-bit signed value is to be saturated into a 16-bit signed
value, the following instruction can be used:
SSAT.W R1, #16, R0
 Similarly, if a 32-bit unsigned value is to saturate into a 16-bit unsigned value,

USAT.W R1, #16, R0

the following instruction can be used:
Examples of Signed Saturation Results
Examples of Unsigned Saturation Results
Input (R0) Output (R1) Q Bit
Input (R0) Output (R1) Q Bit
0x00020000 0x00007FFF Set 0x00020000 0x0000FFFF Set
0x00008000 0x00007FFF Set 0x00008000 0x00008000 Unchanged
0x00007FFF 0x00007FFF Unchanged 0x00007FFF 0x00007FFF Unchanged
0x00000000 0x00000000 Unchanged 0x00000000 0x00000000 Unchanged
0xFFFF8000 0xFFFF8000 Unchanged 0xFFFF8000 0x00000000 Set
0xFFFF7FFF 0xFFFF8000 Set 0xFFFF8001 0x00000000 Set
0xFFFE0000 0xFFFF8000 Set
0xFFFFFFFF 0x00000000 Set
 Several Useful Instructions in the Cortex-M3

 MSR and MRS:

• These two instructions provide access to the special registers in the

Cortex-M3. Here is the syntax of these instructions:

MRS <Rn>, <SReg> ; Move from Special Register

MSR <SReg>, <Rn> ; Write to Special Register

where <SReg> is Special Purpose Register (Ref. Table)

• For example, the following code can be used to set up the process stack
pointer:
LDR R0,=0x20008000 ; new value for Process Stack Pointer (PSP)
MSR PSP, R0
 Several Useful Instructions in the Cortex-M3

 SDIV and UDIV:

 The syntax for signed and unsigned divide
instructions is as follows:
SDIV.W <Rd>, <Rn>, <Rm>
UDIV.W <Rd>, <Rn>, <Rm>
 The result is Rd = Rn/Rm. For example,
LDR R0,=300 ; Decimal 300
MOV R1,#5
UDIV.W R2, R0, R1
This will give you an R2 result of 60 (0x3C)
 Several Useful Instructions in the Cortex-M3
Special Register Names for MRS and MSR Instructions
Symbol Description
IPSR Interrupt status register
EPSR Execution status register (read as zero)
APSR Flags from previous operation
IEPSR A composite of IPSR and EPSR
IAPSR A composite of IPSR and APSR
EAPSR A composite of EPSR and APSR
PSR A composite of APSR, EPSR, and IPSR
MSP Main stack pointer
PSP Process stack pointer
PRIMASK Normal exception mask register
BASEPRI Normal exception priority mask register
Same as normal exception priority mask register, with
BASEPRI_MAX conditional write (new priority level must be higher than the
old level)
Fault exception mask register (also disables normal
FAULTMASK
interrupts)
CONTROL Control register
 REV, REVH and REVSH:

 REV reverses the byte order in a data word, and REVH reverses the byte order

inside a half word.

• For example, if R0 is 0x12345678, in executing the following:
REV R1, R0 REVH R2, R0
• R1 will become 0x78563412, and R2 will be 0x34127856.

 REV and REVH are particularly useful for converting data between big
endian
and little endian.

 REVSH is similar to REVH except that it only processes the lower half word,
and then it sign extends the result.
• For example, if R0 is 0x33448899, running:
 SXTB, SXTH, UXTB, AND UXTH:
• The four instructions SXTB, SXTH, UXTB, and UXTH are used to extend
a byte or half word data into a word.

• The syntax of the instructions is as follows:

SXTB <Rd>, <Rn>
SXTH <Rd>, <Rn>
UXTB <Rd>, <Rn>
UXTH <Rd>, <Rn>

 For SXTB/SXTH, the data are sign extended using bit[7]/bit[15] of Rn. With
UXTB and UXTH, the value is zero extended to 32-bit.

• For example, if R0 is 0x55AA8765: SXTB R1, R0 ; R1 = 0x00000065

SXTH R1, R0 ; R1 = 0xFFFF8765

UXTB R1, R0 ; R1 = 0x00000065
UXTH R1, R0 ; R1 = 0x00008765
 Reverse Bit:
• The RBIT instruction reverses the bit order in a data word.
• The syntax is as follows:
RBIT.W <Rd>, <Rn>
 This instruction is very useful for processing serial bit streams in data
communications.
For example, if R0 is 0xB4E10C23
(binary value 1011_0100_1110_0001_0000_1100_0010_0011),
executing:
RBIT.W R0, R1
R0 will become 0xC430872D
(binary value 1100_0100_0011_0000_1000_0111_0010_1101).
 Bit Field Clear and Bit Field Insert

 Bit Field Clear (BFC) : Clears 1-31 adjacent bits in any position of a register.
 The syntax of the instruction is as follows:
BFC.W <Rd>, <#lsb>, <#width>
• For example,
LDR R0,=0x 1234FFFF BFC.W R0, #4, #8
This will give R0 = 0x1234F00F.
 Bit Field Insert (BFI): Copies 1-31 bits (#width) from one register to any location
(#lsb) in another register.
 The syntax is as follows:
BFI.W <Rd>, <Rn>, <#lsb>, <#width>
• For example,
LDR R0,=0x12345678
LDR R1,=0x3355AACC
BFI.W R1, R0, #8, #16 ; Insert R0[15:0] to R1[23:8]
This will give R1 = 0x335678CC.
UBFX and SBFX:
 UBFX and SBFX are the unsigned and signed bit field extract instructions.
 The syntax of the instructions is as follows:
UBFX.W <Rd>, <Rn>, <#lsb>, <#width>
SBFX.W <Rd>, <Rn>, <#lsb>, <#width>
 UBFX extracts a bit field from a register starting from any location (specified by #lsb)
with any width (specified by #width), zero extends it, and puts it in the destination
register. For example,
LDR R0,=0x5678ABCD
UBFX.W R1, R0, #4, #8
This will give R1 = 0x000000BC.
 Similarly, SBFX extracts a bit field, but its sign extends it before putting it in a
destination register. For example,
LDR R0,=0x5678ABCD
SBFX.W R1, R0, #4, #8
This will give R1 = 0xFFFFFFBC.
LDRD and STRD:
 The two instructions LDRD and STRD transfer two words of data from or into two

registers. The syntax of the instructions is as follows:

LDRD.W <Rxf>, <Rxf2>, [Rn, #+/-offset]{!} ; Pre-indexed
LDRD.W <Rxf>, <Rxf2>, [Rn], #+/-offset ; Post-indexed
where <Rxf> is the first destination/source register and <Rxf2> is the second
destination/source register.
STRD.W <Rxf>, <Rxf2>, [Rn, #+/-offset]{!} ; Pre-indexed
STRD.W <Rxf>, <Rxf2>, [Rn], #+/-offset ; Post-indexed
• For example, the following code reads a 64-bit value located in memory address
0x1000 into
R0 and R1:
LDR R2,=0x1000
LDRD.W R0, R1, [R2] ; This will gives R0 =memory[0x1000];
R1 = memory[0x1004]
LDRD and STRD:
 Similarly, we can use STRD to store a 64-bit value in memory.
 In the following example, preindexed addressing mode is used:
LDR R2,=0x1000 ; Base address
STRD.W R0, R1, [R2, #0x20] ; This will gives memory[0x1020] = R0;
memory[0x1024] = R1
 Table Branch Byte and Table Branch Halfword
 Table Branch Byte (TBB) and Table Branch Halfword (TBH) are for
implementing branch tables.
 The TBB instruction uses a branch table of byte size offset, and TBH uses a branch

table
of half word offset.
 Since the bit 0 of a program counter is always zero, the value in the branch table is
multiplied by two before it’s added to PC.
 Furthermore, because the PC value is the current instruction address plus four,
the branch range for TBB is (2 x 255) + 4 = 514, and
the branch range for TBH is (2 x 65535) + 4 = 131074.
 Both TBB and TBH support forward branch only. TBB has this general syntax:
TBB.W [Rn, Rm]

where Rn is the base memory offset and Rm is the branch table index.
Table Branch Byte and Table Branch Halfword

TBB Operation
 Table Branch Byte and Table Branch Halfword
 For TBH instruction, the process is similar except the memory location of the
branch table item is located at Rn + 2 x Rm and the maximum branch offset is
higher. Again, we assume that Rn is set to PC.

 If Rn in the table branch instruction is set to R15, the value used for Rn will be

PC + 4 because of the pipeline in the processor.

TBH Operation

 These two instructions are more likely to be used by a C compiler to generate code for
switch (case) statements.
 Miscellaneous Instruction
Other 16-Bit Instructions

Instruction Function
SVC Supervisor call

SEV Send event

WFE Sleep and wait for event

WFI Sleep and wait for interrupt

Breakpoint; if debug is enabled, it will enter debug mode (halted), or if

BKPT debug monitor exception is enabled, it will invoke the debug exception;
otherwise, it will invoke a fault exception

NOP No operation
Enable PRIMASK (CPSIE i)/FAULTMASK (CPSIE f ) register (set the
CPSIE
register to 0)
Disable PRIMASK (CPSID i)/ FAULTMASK (CPSID f ) register (set the
CPSID
register to 1)
 Miscellaneous Instruction
Other 32-Bit Instructions

Instruction Function
Instruction Function

LDREX Exclusive load word

MSR
Move to special register from
LDREXH Exclusive load half word general-purpose register

LDREXB Exclusive load byte NOP No operation

STREX Exclusive store word SEV Send event

STREXH Exclusive store half word WFE Sleep and wait for event

STREXB Exclusive store byte WFI Sleep and wait for interrupt

CLREX Clear the local exclusive access ISB Instruction synchronization barrier
record of local processor
DSB Data synchronization barrier
MRS Move special register to general-
purpose register DMB Data memory barrier
Thank You