ARM MICROCONTROLLER & EMBEDDED

SYSTEMS (17EC62)

ARM Cortex M3 Instruction Sets and Programming

(Lecture-4)
(Lecture-1)
ARM Instruction Sets

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Assembly Basics: Assembler Language: Basic Syntax
In assembler code, the following instruction formatting is commonly used:
label opcode operand1, operand2, ...; Comments
 The label is optional. Some of the instructions might have a label in front of

them so that the address of the instructions can be determined using the
label.
 Then, the opcode (the instruction) followed by a number of operands.
 Normally, the first operand is the destination of the operation. The
number of operands in an instruction depends on the type of instruction, and

the syntax format of the operand can also be different.

For example, immediate data are usually in the form #number, as shown here:
 MOV R0, #0x12 ; Set R0 = 0x12 (hexadecimal) 2
 Define constants using EQU, and then use them inside your program code.

For example,
NVIC_IRQ_SETEN0 EQU 0xE000E100 NVIC_IRQ0_ENABLE EQU 0x1

LDR R0,=NVIC_IRQ_SETEN0 ; LDR here is a pseudo-instruction that convert to a

PC relative load by assembler.

MOV R1,#NVIC_IRQ0_ENABLE ; Move immediate data to register
STR R1,[R0] ; Enable IRQ 0 by writing R1 to address in R0

 Data definition directives are available for insertion of constants inside assembly code.

 DCI (Define Constant Instruction) can be used to code an instruction if the assembler
cannot generate the exact instruction that you want and if you know the binary code for
the instruction. 3
DCB (Define Constant Byte) for byte size constant values, such as characters
 Define Constant Data (DCD) for word size constant values to define binary data in
your code.
LDR R3,=MY_NUMBER ; Get the memory address value of MY_NUMBER
LDR R4,[R3] ; Get the value code 0x12345678 in R4LDR R0,=HELLO_TXT
; Get the starting memory address of HELLO_TXT
BL PrintText ; Call a function called PrintText to display string

MY_NUMBER DCD 0x12345678 HELLO_TXT

DCB "Hello\n",0 ; null terminated string
Note that the assembler syntax depends on which assembler tool you are using.

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 Assembler Language: Use Of Suffixes
 For the Cortex-M3, the conditional execution suffixes are usually used for

branch instructions.

 However, other instructions can also be used with the conditional

execution suffixes if they are inside an IF-THEN instruction block.

 In those cases, the S suffix and the conditional execution suffixes can be

Suffix Description
used at the same time.
Update Application Program Status register (APSR) (flags); for
S
example: ADDS R0, R1 ; this will update APSR

Conditional execution; EQ = Equal, NE = Not Equal, LT = Less

EQ, NE, LT, GT, Than, GT = Greater Than, and so forth. For example:
and so on BEQ <Label> ; Branch if equal
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 Assembler Language: Unified Assembler Language
 To support and get the best out of the Thumb®-2 instruction set, the Unified
Assembler Language (UAL) was developed to allow selection of 16-bit and 32-
bit instructions and to make it easier to port applications between ARM code and
Thumb code by using the same syntax for both.
ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax

ADD R0, R0, R1 ; Equivalent instruction using UAL syntax

 The traditional Thumb syntax can still be used. The choice between whether the
instructions are interpreted as traditional Thumb code or the new UAL syntax is
normally defined by the directive in the assembly file.

 For example, with ARM assembler tool, a program code header with “CODE16”

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directive implies the code is in the traditional Thumb syntax, and “THUMB”
 Assembler Language: Unified Assembler Language
 With reusing traditional Thumb is that some instructions change the flags in APSR,
even if the S suffix is not used. However, when the UAL syntax is used, whether the

instruction changes the flag depends on the S suffix. For example,

AND R0, R1 ; Traditional Thumb syntax

ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)

 With the new instructions in Thumb-2 technology, some of the operations can be
handled by either a Thumb instruction or a Thumb-2 instruction. For example, R0 =
R0 + 1 can be implemented as a 16-bit Thumb instruction or a 32-bit Thumb-2
instruction. With UAL, you can specify which instruction you want by adding
suffixes:
ADDS R0, #1 ; Use 16-bit Thumb instruction by default for smaller size
ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
 Instruction Descriptions
 Till now we have gone through different set of 16-bit, 32-bit instructions and

also different instructions that are not supported by Cortex-M3

microcontroller.

 Here, we shall understand some of the commonly used syntax for ARM
assembly code.
 For better understanding let me categorize these instructions into following 4

categories:

1. Moving Data instructions

2. Data Processing Instructions

3. Execution Flow control instructions and

 1. Moving Data instructions
 One of the most basic functions in a processor is transfer of data. In the Cortex-M3,

data transfers can be of one of the following types:

• Moving data between register and register
• Moving data between memory and register
• Moving data between special register and register
• Moving an immediate data value into a register

 The command to move data between registers is MOV (move). For example,
moving data from register R3 to register R8 looks like this:
MOV R8, R3

 Another instruction can generate the negative value of the original data; it is called
MVN (move negative).
 1. Moving Data instructions

 The basic instructions for accessing memory are Load and Store.

Load (LDR) transfers data from memory to registers, and Store transfers data from
registers to memory.
 The transfers can be in different data sizes (byte, half word, word, and double
word), multiple Load and Store operations can be combined into single
instructions called LDM (Load Multiple) and STM (Store Multiple).

 The exclamation mark (!) in the instruction specifies whether the register Rd
should be updated after the instruction is completed.
For example, if R8 equals 0x8000:
STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store ;
(increment by 4 words) STMIA.W R8 , {R0-R3} ; R8 unchanged
after store
 Instruction List
16-Bit Load and Store Instructions
Instruction Function
LDR Load word from memory to register
LDRH Load half word from memory to register
LDRB Load byte from memory to register
Load half word from memory, sign extend it, and put it in
LDRSH
register
LDRSB Load byte from memory, sign extend it, and put it in register
STR Store word from register to memory
STRH Store half word from register to memory
STRB Store byte from register to memory
LDM/LDMIA Load multiple/Load multiple increment after
STM/STMIA Store multiple/Store multiple increment after
PUSH Push multiple registers

POP Pop multiple registers

32-Bit Load and Store Instructions
Instruction Function
LDR Load word data from memory to register
LDRT Load word data from memory to register with unprivileged access
LDRB Load byte data from memory to register
LDRBT Load byte data from memory to register with unprivileged access
LDRH Load half word data from memory to register
LDRHT Load half word data from memory to register with unprivileged access
LDRSB Load byte data from memory, sign extend it, and put it to register
LDRSBT Load byte data from memory with unprivileged access, sign extend it, and put it to register
LDRSH Load half word data from memory, sign extend it, and put it to register
LDRSHT Load half word data from memory with unprivileged access, sign extend it, and put it to register
LDM/LDMIA Load multiple data from memory to registers
LDMDB Load multiple decrement before
LDRD Load double word data from memory to registers
STR Store word to memory
STRT Store word to memory with unprivileged access
STRB Store byte data to memory
STRBT Store byte data to memory with unprivileged access
STRH Store half word data to memory
STRHT Store half word data to memory with unprivileged access
STM/STMIA Store multiple words from registers to memory
STMDB Store multiple decrement before
STRD Store double word data from registers to memory
PUSH Push multiple registers
POP Pop multiple registers
 Commonly Used Memory Access Instructions

Example Description

LDRB Rd, [Rn, #offset] Read byte from memory location Rn + offset

LDRH Rd, [Rn, #offset] Read half word from memory location Rn + offset

LDR Rd, [Rn, #offset] Read word from memory location Rn + offset
LDRD Rd1,Rd2, [Rn,
#offset] Read double word from memory location Rn + offset

STRB Rd, [Rn, #offset] Store byte to memory location Rn + offset

STRH Rd, [Rn, #offset] Store half word to memory location Rn + offset

STR Rd, [Rn, #offset] Store word to memory location Rn + offset

STRD Rd1,Rd2, [Rn,
#offset] Store double word to memory location Rn + offset
Multiple Memory Access Instructions

Example Description
Read multiple words from memory location specified by Rd;
LDMIA Rd!,<reg list> address increment after (IA) each transfer (16-bit Thumb
instruction)
Store multiple words to memory location specified by Rd;
STMIA Rd!,<reg list> address increment after (IA) each transfer (16-bit Thumb
instruction)

LDMIA.W Rd(!),<reg list> Read multiple words from memory location specified by Rd;
address increment after each read (.W specified it is a 32-bit
Thumb-2 instruction)
Read multiple words from memory location specified by Rd;
LDMDB.W Rd(!),<reg list> address Decrement Before (DB) each read (.W specified it is a
32-bit Thumb-2 instruction)
Write multiple words to memory location specified by Rd;
STMIA.W Rd(!),<reg list> address increment after each read (.W specified it is a 32-bit
Thumb-2 instruction)
Write multiple words to memory location specified by Rd;
STMDB.W Rd(!),<reg list>
address DB
 PREINDEXING and POSTINDEXING.
 For preindexing, the register holding the memory address is adjusted. The
memory transfer then takes place with the updated address. For example,
LDR.W R0,[R1, #offset]! ; Read memory[R1+offset], with R1
update to R1+offset
 The use of the “!” indicates the update of base register R1. The “!” is optional;
without it, the instruction would be just a normal memory transfer with offset from a

base address.
 The preindexing memory access instructions include load and store instructions of
Examples of Preindexing Memory Access Instructions
various transfer sizes
Example Description
LDR.W Rd, [Rn, #offset]!
LDRB.W Rd, [Rn, #offset]! Preindexing load instructions for various sizes (word, byte, halfword,
LDRH.W Rd, [Rn, #offset]! and double word)
LDRD.W Rd1, Rd2,[Rn, #offset]!
LDRSB.W Rd, [Rn, #offset]!
Preindexing load instructions for various sizes with sign extend (byte,
LDRSH.W Rd, [Rn, #offset]! half word)
STR.W Rd, [Rn, #offset]!
STRB.W Rd, [Rn, #offset]!
Preindexing store instructions for various sizes (word, byte, halfword,
STRH.W Rd, [Rn, #offset]!
and double word)
STRD.WRd1, Rd2,[Rn, #offset]!
 Postindexing memory access instructions carry out the memory transfer using the base address
specified by the register and then update the address register afterward. For example,
LDR.W R0,[R1], #offset ; Read memory[R1], with R1 updated to R1+offset

 When a postindexing instruction is used, there is no need to use the “!” sign, because all
postindexing instructions update the base address register, whereas in preindexing you might choose
whether to update the base address register or not.
Examples of Postindexing Memory Access Instructions

Example Description
LDR.W Rd, [Rn] #offset
LDRB.W Rd, [Rn] #offset Postindexing load instructions for various sizes (word,
LDRH.W Rd, [Rn] #offset byte, half word, and double word)
LDRD.W Rd1, Rd2, [Rn] #offset
LDRSB.W Rd, [Rn] #offset Postindexing load instructions for various sizes with sign
LDRSH.W Rd, [Rn] #offset extend (byte, half word)
STR.W Rd, [Rn] #offset
STRB.W Rd, [Rn] #offset Postindexing store instructions for various sizes (word,
STRH.W Rd, [Rn] #offset
byte, half word, and double word)
STRD.W Rd1, Rd2, [Rn] #offset
 Two other types of memory operation are stack PUSH and stack POP. For example,

PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into stack memory
POP {R2,R3} ; Pop R2 and R3 from stack

 Usually a PUSH instruction will have a corresponding POP with the same register list, but
this is not always necessary. For example, a common exception is when POP is used as a
function return:
PUSH {R0-R3, LR} ; Save register contents at beginning of subroutine
 In this case, instead of popping the LR register back and then branching to the address in
LR, we POP the address value directly in the program counter.

 In the Cortex-M3 to access special registers, we use the instructions MRS and MSR. For
example,
MRS R0, PSR ; Read Processor status word into R0
MSR CONTROL, R1 ; Write value of R1 into control register
 Unless you’re accessing the APSR, you can use MSR or MRS to access other special |
registers only in privileged mode.
 Moving immediate data into a register is a common thing to do. For example,
you might want to access a peripheral register, so you need to put the address
value into a register beforehand. For small values (8 bits or less), you can use
MOVS (move).
 For example,
MOVS R0, #0x12 ; Set R0 to 0x12

 For a larger value (over 8 bits), you might need to use a Thumb-2 move
instruction. For example,
MOVW.W R0, #0x789A ; Set R0 to 0x789A

Or if the value is 32-bit, you can use two instructions to set the upper and lower
halves:
MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A
MOVT. W R0,#0x3456 ; Set R0 upper half to 0x3456. Now R0=
0x3456789A
2. Data Processing Instructions

 The Cortex-M3 provides many different instructions for data processing. Many

data operation instructions can have multiple instruction formats.

 For example, an ADD instruction can operate between two registers or between
one register and an immediate data value:
ADD R0, R0, R1 ; R0 = R0 + R1
ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
ADD.W R0, R1, R2 ; R0 = R1 + R2
 These are all ADD instructions, but they have different syntaxes and binary
coding.

 With the traditional Thumb instruction syntax, when 16-bit Thumb code is used,
2. Data Processing Instructions

 To separate the two different operations, the S suffix should be used if the
following operation depends on the flags:
ADD.W R0, R1, R2 ; Flag unchanged
ADDS.W R0, R1, R2 ; Flag change

 Aside from ADD instructions, the arithmetic functions that the Cortex-M3
supports include subtract (SUB), multiply (MUL), and unsigned and signed
divide (UDIV/SDIV).
 Instruction List
16-Bit Data Processing Instructions
Instruction Function
ADC Add with carry
ADD Add
ADR Add PC and an immediate value and put the result in a register
AND Logical AND
ASR Arithmetic shift right
BIC Bit clear (Logical AND one value with the logic inversion of another value)
Compare negative (compare one data with two’s complement of another data
CMN
and update flags)
CMP Compare (compare two data and update flags)
Copy (available from architecture v6; move a value from one high or low
CPY
register to another high or low register); synonym of MOV instruction
EOR Exclusive OR
LSL Logical shift left
LSR Logical shift right

MOV Move (can be used for register-to-register transfers or loading immediate data)
MUL Multiply
MVN Move NOT (obtain logical inverted value)
NEG Negate (obtain two’s complement value), eq
 Instruction List
16-Bit Data Processing Instructions Continued

Instruction Function
ORR Logical OR
RSB Reverse subtract
ROR Rotate right
SBC Subtract with carry
SUB Subtract
TST Test (use as logical AND; Z flag is updated but AND result is not stored)
REV Reverse the byte order in a 32-bit register (available from architecture v6)
REV16 Reverse the byte order in each 16-bit half word of a 32-bit register
(available from architecture v6)
REVSH Reverse the byte order in the lower 16-bit half word of a 32-bit register
and sign extends the result to 32 bits (available from architecture v6)
SXTB Signed extend byte (available from architecture v6)
SXTH Signed extend half word (available from architecture v6)
UXTB Unsigned extend byte (available from architecture v6)
UXTH Unsigned extend half word (available from architecture v6) 7
 Instruction List
32-Bit Data Processing Instructions
Instruction Function Instruction Function

ADC Add with carry LSL Logical shift left

ADD Add
LSR Logical shift right
ADDW Add wide (#immed_12)
Add PC and an immediate value MLA Multiply accumulate
ADR
and put the result in a register MLS Multiply and subtract
AND Logical AND
MOV Move
ASR Arithmetic shift right
Bit clear (logical AND one value Move wide (write a 16-bit
MOVW
BIC with the logic inversion of another immediate value to register)
value) Move top (write an immediate value
BFC Bit field clear MOVT to the top half word of destination
reg)
BFI Bit field insert
Compare negative (compare one MVN Move negative
CMN data with two’s complement of MUL Multiply
another data and update flags)
Compare (compare two data and ORR Logical OR
CMP
update flags)
ORN Logical OR NOT
CLZ Count leading zero
RBIT Reverse bit
EOR Exclusive OR
REV Byte reverse word
 Instruction List
32-Bit Data Processing Instructions Continued
Instruction Function Instruction Function
REV16 Byte reverse packed half word SUBW Subtract wide (#immed_12)
REVSH Byte reverse signed half word SXTB Sign extend byte
ROR Rotate right SXTH Sign extend half word
RSB Reverse subtract
RRX Rotate right extended TEQ Test equivalent (use as logical
exclusive OR; flags are updated but
SBC Subtract with carry result is not stored)
Test (use as logical AND; Z flag is
SBFX Signed bit field extract TST updated but AND result is not
stored)
SDIV Signed divide
UBFX Unsigned bit field extract
SMLAL Signed multiply accumulate long
UDIV Unsigned divide
SMULL Signed multiply long UMLAL Unsigned multiply accumulate long
SSAT Signed saturate UMULL Unsigned multiply long
USAT Unsigned saturate
SBC Subtract with carry
UXTB Unsigned extend byte
SUB Subtract
UXTH Unsigned extend half word
Examples of Arithmetic Instructions
Instruction Operation
ADD Rd, #immed ; Rd = Rd + #immed
ADD operation
ADD Rd, Rn, # immed ; Rd = Rn + #immed
ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
ADC Rd, Rd, Rm ; Rd = Rd + Rm + carry ADD with carry
; Rd = Rd + #immed +
ADC Rd, #immed carry
ADD register with 12-bit immediate
ADDW Rd, Rn,#immed ; Rd = Rn + #immed value
SUB Rd, Rn, Rm ; Rd = Rn - Rm
SUB Rd, #immed ; Rd = Rd - #immed SUBTRACT
SUB Rd, Rn,#immed ; Rd = Rn - #immed
SBC Rd, Rm ; Rd = Rd - Rm - borrow
; Rd = Rn - #immed -
SBC.W Rd, Rn, #immed borrow SUBTRACT with borrow (not carry)
SBC.W Rd, Rn, Rm ; Rd = Rn - Rm - borrow
RSB.W Rd, Rn, #immed ; Rd = #immed -Rn
Reverse subtract
RSB.W Rd, Rn, Rm ; Rd = Rm - Rn
MUL Rd, Rm ; Rd = Rd * Rm
Multiply
MUL.W Rd, Rn, Rm ; Rd = Rn * Rm
UDIV Rd, Rn, Rm ; Rd = Rn/Rm Unsigned and signed divide
SDIV Rd, Rn, Rm ; Rd = Rn/Rm
 The Cortex-M3 also supports 32-bit multiply instructions and multiply accumulate
Instructions that give 64-bit results
Instruction Operation
SMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm 32-bit multiply instructions for
SMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm signed values

UMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm 32-bit multiply instructions for

UMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm unsigned values

 Another group of data processing instructions are the logical operations

instructions and logical operations such as AND, ORR (or), and shift and rotate
functions.

 These instructions can be used with or without the “S” suffix to determine if the
APSR should be updated.

 If UAL syntax is used and if “S” suffix is not used, the 32-bit version of the
instructions would be selected as all of the 16-bit logic operation instructions
update APSR.
 Logic Operation Instructions

Instruction Operation

AND Rd, Rn ; Rd = Rd & Rn

. AND.W Rd, Rn, #immed ; Rd = Rn & #immed Bitwise AND

AND.W Rd, Rn, Rm ; Rd = Rn & Rd

Logic Operation Instructions continued

Instruction Operation
ORRRd, Rn ; Rd = Rd | Rn

ORR.W Rd, Rn,#immed ; Rd = Rn | #immed Bitwise OR

ORR.W Rd, Rn, Rm ; Rd = Rn | Rd

BIC Rd, Rn ; Rd = Rd & (~Rn)

BIC.W Rd, Rn,#immed ; Rd = Rn &(~#immed) Bit clear

BIC.W Rd, Rn, Rm ; Rd = Rn &(~Rd)

ORN.W Rd, Rn,#immed ; Rd = Rn | (~#immed)

Bitwise OR NOT
ORN.W Rd, Rn, Rm ; Rd = Rn | (~Rd)

EOR Rd, Rn ; Rd = Rd A Rn

EOR.W Rd, Rn,#immed ; Rd = Rn | #immed Bitwise Exclusive OR

EOR.W Rd, Rn, Rm ; Rd = Rn | Rd

Thank You