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18 20210619 Computer Architecture Super Pipelined VLIW Processor Architecture

The document discusses superpipelined and VLIW (Very Long Instruction Word) processor architectures, highlighting the DEC 21064-A superpipelined processor's features and performance. It explains the design goals of VLIW, including reduced hardware complexity and power consumption, as well as the advantages of horizontal and vertical microcoding. The VLIW architecture is noted for its simplicity and effectiveness in scientific applications due to predictable program behavior.

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Aritra Das
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10 views15 pages

18 20210619 Computer Architecture Super Pipelined VLIW Processor Architecture

The document discusses superpipelined and VLIW (Very Long Instruction Word) processor architectures, highlighting the DEC 21064-A superpipelined processor's features and performance. It explains the design goals of VLIW, including reduced hardware complexity and power consumption, as well as the advantages of horizontal and vertical microcoding. The VLIW architecture is noted for its simplicity and effectiveness in scientific applications due to predictable program behavior.

Uploaded by

Aritra Das
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Computer Architecture

(PCC CS-402)
Processor Architecture
Super pipelined, VLIW

May 12, 2025


Superpipelined processor
■ Superpipelined processor of degree n, the pipeline
cycle is 1/n of the base cycle.
■ The minimum time required to execute N instructions
of degree n with k stages is:

■ The potential speedup is:

■ Overlapping multiple operations running concurrently


on common hardware.

May 12, 2025 2


Superpipelined processor: DEC 21064-A

Architecture of DEC 21064-A superpipelined processor

May 12, 2025 3


Superpipelined processor: DEC 21064-A

DEC 21064-A superpipelined processor

May 12, 2025 4


Superpipelined processor: DEC 21064-A
■ DEC 21064-A features:
● It was designed by Digital Equipment Corporation in
1990 based on Alpha AXP architecture.
● 64-bit superpipelined superscalar processor.
● Clock rate is 150 MHz.
● Several design issues:
 Speed.
 Multiple instruction issue.
 Multiprocessor application.
● Thirty two 64-bit integer registers and thirty two 64-bit
floating point registers.
● Integer pipeline has 7 stages and floating point pipeline
has 10 stages.
● Peak performance: 300 MIPS and 150 Mflops at 150
MHz.
● 8 KB direct mapped cache.
May 12, 2025 5
VLIW processor
■ Very Long Instruction Word (VLIW) machine
proposed by Josh Fisher at Yale in 1983.
■ A fixed number of operations are formatted as one big
instruction called a bundle.
● Usually 3 operations are bundled together.
● 1 program counter point 1 bundle (not 1 operation).
■ Multiple functional units (FU) are used concurrently.
■ All functional units share the use of a common larger
register file.
■ Operations to be simultaneously executed by the
functional units are synchronized in VLIW instruction,
typical length of 256-1024 bits per instruction word.
■ Designed based on
● Horizontal micro-coding (discussed later)
● Super scalar processing.

May 12, 2025 6


VLIW processor

VLIW

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Goal of the VLIW design
■ Reduce hardware complexity.
● Less multiple issue hardware
 No dependence checking for instructions within a
bundle
● Simpler instruction dispatch.
■ Reduce power consumption.
■ Shorter cycle time.
■ Fixed format so could decode operations in parallel.
■ Enough FUs for types of operations that can issue in
parallel.
■ Effective CPI reduced.

May 12, 2025 8


VLIW processor
■ Compiler creates each VLIW word.
■ Each instruction specifies multiple operations.
■ Though 3 instructions are bundled together, so
effective CPI becomes 1/3rd .
■ It behave like superscalar machines with following
differences:
● The decoding of VLIW instructions is easier than
superscalar instructions.
● Code density is better when the available ILP is less
than that exploitable by VLIW machine.
● CPI of VLIW machine is lower than superscalar
processor.

May 12, 2025 9


VLIW processor
■ Instruction parallelism and data movement are
specified at compile time.
■ Run time resource scheduling is eliminated.
■ The main advantage of VLIW architecture is its
simplicity in hardware structure and instruction set.
■ The VLIW processor can potentially perform well in
scientific applications where the program behavior
(branch predictions) is more predictable.

May 12, 2025 10


VLIW Vs. Superscalar

May 12, 2025 11


Horizontal Microcode
■ Each microinstruction specifies many different micro-
operations to be performed in parallel.
● Horizontal microprogramming/microcode

May 12, 2025 12


Horizontal Microcode
■ Features:
● Wide memory word.
● One bit in the micro operations field of the
microinstruction is assigned to each micro operation.
● High degree of parallel operations possible.
● Little encoding of control information.
● Each control signal is represented by a bit in the
microinstruction.
● The name horizontal implies fewer control store words
of more bits per word.
● Fewer steps per microinstruction.

May 12, 2025 13


Vertical Microcode
■ Each microinstruction specifies single (or few) micro-
operations to be performed
● Vertical microprogramming/microcode

May 12, 2025 14


Vertical Microcode
■ Features:
● Width is narrow.
● n control signals encoded into (log2n) bits.
● Very limited ability to express parallelism.
● Considerable encoding of control information requires
external memory word decoder to identify the exact
control lines being manipulated.
● A set of true control signal is represented by a shorter
code.
● Vertical microcode may take more control store words
of fewer bits.
● More steps per microinstruction.

May 12, 2025 15

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